Analog Devices ADSP-2192 specifications EP5, EP6, EP7, EP8, EP9

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October 2000

 

 

 

 

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ADSP-2192

 

 

For current information contact Analog Devices at (781) 461-3881

 

 

 

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Table 11. USB DSP Register Definitions (Continued)

 

 

 

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P

 

AddressA

Name

Comment

 

Page C

 

 

E

 

T

 

 

 

 

 

T

A

 

 

 

 

 

0x0C

D

0x18-0x19

DSP Memory Buffer WR Offset

EP5

 

 

 

 

 

 

 

 

 

0x0C

 

0x20-0x23

DSP Memory Buffer Base Addr

EP6

 

 

 

 

 

 

 

0x0C

 

0x24-0x25

DSP Memory Buffer Size

EP6

 

 

 

 

 

 

 

0x0C

 

0x26-0x27

DSP Memory Buffer RD Offset

EP6

 

 

 

 

 

 

 

0x0C

 

0x28-0x29

DSP Memory Buffer WR Offset

EP6

 

 

 

 

 

 

 

0x0C

 

0x30-0x33

DSP Memory Buffer Base Addr

EP7

 

 

 

 

 

 

 

0x0C

 

0x34-0x35

DSP Memory Buffer Size

EP7

 

 

 

 

 

 

 

0x0C

 

0x36-0x37

DSP Memory Buffer RD Offset

EP7

 

 

 

 

 

 

 

0x0C

 

0x38-0x39

DSP Memory Buffer WR Offset

EP7

 

 

 

 

 

 

 

0x0C

 

0x40-0x43

DSP Memory Buffer Base Addr

EP8

 

 

 

 

 

 

 

0x0C

 

0x44-0x45

DSP Memory Buffer Size

EP8

 

 

 

 

 

 

 

0x0C

 

0x46-0x47

DSP Memory Buffer RD Offset

EP8

 

 

 

 

 

 

 

0x0C

 

0x48-0x49

DSP Memory Buffer WR Offset

EP8

 

 

 

 

 

 

 

0x0C

 

0x50-0x53

DSP Memory Buffer Base Addr

EP9

 

 

 

 

 

 

 

0x0C

 

0x54-0x55

DSP Memory Buffer Size

EP9

 

 

 

 

 

 

 

0x0C

 

0x56-0x57

DSP Memory Buffer RD Offset

EP9

 

 

 

 

 

 

 

0x0C

 

0x58-0x59

DSP Memory Buffer WR Offset

EP9

 

 

 

 

 

 

 

0x0C

 

0x60-0x63

DSP Memory Buffer Base Addr

EP10

 

 

 

 

 

 

 

0x0C

 

0x64-0x65

DSP Memory Buffer Size

EP10

 

 

 

 

 

 

 

0x0C

 

0x66-0x67

DSP Memory Buffer RD Offset

EP10

 

 

 

 

 

 

 

0x0C

 

0x68-0x69

DSP Memory Buffer WR Offset

EP10

 

 

 

 

 

 

 

0x0C

 

0x70-0x73

DSP Memory Buffer Base Addr

EP11

 

 

 

 

 

 

 

0x0C

 

0x74-0x75

DSP Memory Buffer Size

EP11

 

 

 

 

 

 

 

0x0C

 

0x76-0x77

DSP Memory Buffer RD Offset

EP11

 

 

 

 

 

 

 

0x0C

 

0x78-0x79

DSP Memory Buffer WR Offset

EP11

 

 

 

 

 

 

 

0x0C

 

0x80-0x81

USB Descriptor Vendor ID

 

 

 

 

 

 

 

 

0x0C

 

0x84-0x85

USB Descriptor Product ID

 

 

 

 

 

 

 

 

0x0C

 

0x86-0x87

USB Descriptor Release Number

 

 

 

 

 

 

 

 

0x0C

 

0x88-0x89

USB Descriptor Device Attributes

 

 

 

 

 

 

 

 

 

Y

 

 

 

 

 

 

 

 

USB DSP Memory Buffer Base Addr Register

assigned to this endpoint.

 

 

 

 

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A

 

 

 

 

 

 

N

 

L

Points to the base address for the DSP memory buffer

• BA[17:0] = Memory Buffer Base Address

 

 

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This information applies to a product under development. Its characteristics and specifications are subject to changePwith-

CREV. PrA A

 

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. E

 

 

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Page 17 Page 19
Image 18
Page 17 Page 19
Contents Preliminary Technical Data 48K words of on-chip RAM on P1, configured as 32K Words on-chip 16-bit RAM for Data Memory and 16KREV. PrA Programmable interval timer generates periodic inter Rupts. a 16-bit count register Tcount is decrementedDSP-DSP Output DSP-DSP Semaphore DSP-DSP InterruptLoop stack interrupt enable ADSP-2192Pliant codecs to the ADSP-2192. The ACLink implements Industry standard AC’97 serial interface AC-LinkADSP-2192 includes a 33MHz, 32 bit bus master PCI Ification. This interface supports the high data ratesDSP, using the REG instruction DSP memory accesses use BAR2 or BAR3 of each funcTion. BAR2 is used to access 24-bit DSP memory BAR3 BAR3 registers appear in on page 14 and TableMode the functions of the registers are mapped as follows Rpci Dmah controller can be programmed to perform scatADSP-2192 without processor intervention. In scat Transmit Channel 0 Bus Master Transactions Tx0 DMA Channel InterruptRegister or memory location within the ADSP-2192. Simi Target accessesI to registers and DSP memory can goRthroughHany function. As long as the Memory Space access BistData Word. BAR3 Mode is typically used for Data Memory IntaPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Unused ReservedA15 7FFC 9FFC0x6-0x7 DSP Memory Buffer RD Offset 0x0-0x3 DSP Memory Buffer Base Addr0x4-0x5 DSP Memory Buffer Size 0x8-0x9 DSP Memory Buffer WR OffsetEP7 EP5EP6 EP8Release Number is 0x0100, which corresponds to Descriptor command is contained in this register.Release Number returned in the GET Device Device-specific attributes returned in the GETUSB EP6 NAK USB EP4 NAKUSB EP5 NAK USB EP7 NAKA21 ThisR registerHprovides information as the total size ISE = Current interrupt is for a Setup tokenINT = Active interrupt for the 8052 MCU Fixed Endpoints Control Endpoint0x01 0x02 0x00 ADIREV. PrA A23 USB Mcucode XXXWValue L USB RegioBRequest 0xA0 AddressWValue H A27 If for some reason the host sends more data than the max Packetsize, theNUSB core accepts it, as long as there isSufficientCroom in theAFIFO An active lowIRST input to be derived from PCI RST Power themselves and the ADSP-2192 completely downDeassertion of PDW1 high causes a wake-up of the DSP Pmeen output from the Combo Master shouldFifo Eslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only SMSelIBit 3 Stereo / Mono Select AC’97 ModeInterfaces reset the DSP under their control as needed Is shown as a no connect in on page 33 theseADSP-2192 Boot Process Flow ADSP-2192 can be clocked by a crystal oscillator. If aForEthis configuration.T Manufacturer.I a parallel-resonant, fundamental frequencyRmicroprocessorH -grade 24.576 MHz crystal should be used Tion-level simulator a C/C++ compiler and a C/C++ Run-time library that includes DSP and mathematical funcA35 AD2 AD0AD1 AD3Clkrun Devsel Frame GNT Idsel Intab CBE0 CBE1 CBE2 CBE3 CLK130 131 128 PCI / ISA InterruptPcignd IrdyPAR PcivddEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Mode Select Emulator Logic ResetEmulator Data Output Acvaux Aiognd Avdd Ctrlaux Ctrlvdd IgndIvdd Rvaux Rvdd Specifications are subject to change TBDInput Capacitance6 FIN=1 MHz Supply Current Dynamic @ 160 Mips InternalSupply Current Idle VIN=2.5VWrite Data Setup to IOW Rising AEN Setup to IOR / IOW FallingAddress Setup to IOR / IOW Falling IOR / IOW Strobe Width 100Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
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