Analog Devices ADSP-2192 specifications If for some reason the host sends more data than the max

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ADSP-2192
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If for some reason the host sends more data than the max-
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packetsize, theNUSB core accepts it, as long as there is
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sufficientCroom in theAFIFO.
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	T	A

Since the DSPDcontrols the read pointer, it must perform a

similar calculation to determine if there is sufficient data in the FIFO to begin processing. Once it has consumed some amount of data, the DSP will need to update the Memory Buffer Read Offset register.

IN Transactions (Host <- Device)

When an IN transaction arrives for a particular endpoint, the USB core once again computes how much read data is available in the FIFO. It also determines if the amount of read data is greater than or equal to the maxpacketsize. If both conditions are met, the USB core will transfer the data. Upon receiving ACK from the host, the USB core updates the Memory Buffer Read Offset register.

If the amount of read data is less than the maxpacketsize (a short packet), the USB core determines whether to send the data based upon a NAK count limit. This is a 4-bit field in

Table 23. Sub-ISA (PCI) Pin Descriptions

October 2000

the Endpoint Stall Policy register that can be programmed with a value indicating how many NAK's should be sent prior to transmitting a short packet. This allows flexibility in determining how IRPs are retired via short packets.

Since the DSP controls the write pointer, it must determine if there is sufficient room in the FIFO for placing new data. Once it has completed writes to the FIFO, it needs to update the Memory Buffer Write Offset register.

Sub-ISA Interface

In systems which combine the ADSP-2192 chip with other devices on a single PCI interface, the ADSP-2192 Sub-ISA mode is used to provide a simpler interface (to a PCI func- tion ASIC), which bypasses the ADSP-2192’s PCI interface.

In this mode, the Combo Master assumes all responsibility for interfacing the function to the PCI bus, including provi- sion of Configuration Space registers for the ADSP-2192 system as a separate PnP function. In Sub-ISA Mode the PCI Pins are reconfigured for ISA operation, as follows.

Pin Name	PCI Direction1		ISA Alias	ISA Direction	ISA Description.
AD[15:0]	In/Out		ISAD[15:0]	In/Out	Data
AD[18:16]	In/Out		ISAA[3:1]	In	Register Address
AD[31:22]	In/Out		Unused	In	Tie to GND in Sub-ISA Mode
	In			In	Reset
RST			RST
	In/Out			In	Write Strobe
CBE0			IOW
	In/Out			In	Read Strobe
CBE1			IOR
	In/Out			In	Chip Select (Access Enable)
CBE2			AEN
	Out (o/d)	IRQ		Out	(CMOS) Interrupt (Active High)
INTA
AD21	In/Out			In	PCI D-state MSB (inverted) Power-Down
			PDW1
AD20	In/Out			In	PCI D-state LSB (inverted) Power-Down
			PDW0
AD19	In/Out		PME_EN	In	PME Enable
	Out (o/d)			Out (o/d)	Power Management Event
PME			PMERQ
CLK	In		Unused	In	Tie to GND in Sub-ISA Mode
	In/Out		IOCHRDY	Out	IO Ready
CLKRUN
CLKRUN	Out	IOCHRDY		Out	Acknowledge

1o/d = Open Drain

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In Sub-ISA mode, the ADSP-2192’s PCI protocol is		possible only to the PCI Base Address 4 (BAR4) Registers						R
replaced with an ISA-like, asynchronous protocol con-							A
		(the InDirect Access Registers). The Sub-ISA Address Map
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trolled by the strobes IOR, IOW and AEN. Access is		is shown in Table 23 on page 28.		M				A
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	This information applies to a product under development. Its characteristics and specifications are subject to changePwith-			CREV. PrA A
	out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.		E				T
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