Analog Devices ADSP-2192 specifications Mode the functions of the registers are mapped as follows

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For current information contact Analog Devices at (781) 461-3881

ADSP-2192

 

 

 

 

 

 

 

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samples to and from DSP memory, the

 

Scatter-gather DMA uses four registers. In scatter-gather

 

 

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mode the functions of the registers are mapped as follows:

RPCI DMAH controller can be programmed to perform scat-

 

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terE-gather DMA.T This mode allows the data to be split up

 

 

 

 

 

 

 

 

 

 

 

 

 

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Table 4. Register-Mapping in Scatter-Gather Mode

 

 

 

 

in memory,D and yet be able to be transferred to and from the

 

 

 

 

 

ADSP-2192 without processor intervention. In scat-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Standard Circular Buffer

Scatter-Gather Mode

 

 

 

 

ter-gather mode, the DMA controller can read the memory

 

 

 

 

 

address and word count from an array of buffer descriptors

 

Mode

Function

 

 

 

 

 

 

 

 

 

called the Scatter-Gather Descriptor (SGD) table. This

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Address

SGD Table Pointer

 

 

 

 

 

allows the DMA engine to sustain DMA transfers until all

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

buffers in the SGD table are transferred.

 

Current Address

SGD Current Pointer

 

 

 

 

To initiate a scatter-gather transfer between memory and

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

the ADSP-2192, the following steps are involved:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Count

SGD Pointer

 

 

 

 

 

 

 

1.

Software driver prepares a SGD table in system mem-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ory. Each descriptor is eight bytes long and consists of

 

Current Count

Current SGD Count

 

 

 

 

 

an address pointer to the starting address and the trans-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

fer count of the memory buffer to be transferred. In any

 

In either mode of operation, interrupts can be generated

 

 

 

given SGD table, two consecutive SGDs are offset by

 

 

 

 

 

based upon the total number of bytes transferred. Each

 

 

 

eight bytes and are aligned on a 4-byte boundary. Each

 

 

 

 

 

channel has two 24-bit registers to count the bytes trans-

 

 

 

SGD contains:

 

 

 

 

 

 

 

 

 

ferred and generate interrupts as appropriate. The

 

 

 

 

 

 

a. Memory Address (Buffer Start) – 4 bytes

 

 

 

 

 

 

 

 

Interrupt Base Count register specifies the number of bytes

 

 

 

b.

Byte Count (Buffer Size) – 3 bytes

 

to transfer prior to generating an interrupt. The Interrupt

 

 

 

c.

End of Linked List (EOL) – 1 bit (MSBit)

 

Count register specifies the current number left prior to

 

 

 

 

generating the interrupt. When the Interrupt Count register

 

 

 

d. Flag – 1 bit (MSBit – 1)

 

 

 

 

 

reaches zero, a PCI interrupt can be generated. Addition-

 

2.

Initialize DMA control registers with transfer specific

 

 

 

ally, the Interrupt Count register will be reloaded from the

 

 

 

information such as number of total bytes to transfer,

 

Interrupt Base Count and continue counting down for the

 

 

 

direction of transfer, etc.

 

 

 

next interrupt.

 

 

 

 

 

 

 

 

 

3.

Software driver initializes the hardware pointer to the

 

PCI Interrupts

 

 

 

 

 

 

 

 

 

 

 

SGD table.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

There are a variety of potential sources of interrupts to the

 

4.

Engage scatter-gather DMA by writing the start value

 

 

 

PCI host besides the bus master DMA interrupts. A single

 

 

 

to the PCI channel Control/Status register.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

interrupt pin, INTA is used to signal these interrupts back

 

5.

The ADSP-2192 will then pull in samples as pointed to

 

 

 

to the host. The PCI Interrupt Register consolidates all of

 

 

 

by the descriptors as needed by the DMA engine.

 

 

 

 

 

the possible interrupt sources; the bits of this register are

 

 

 

When the EOL is reached, a status bit will be set and

 

 

 

 

 

shown in Table 5 on page 9. The register bits are set by the

 

 

 

the DMA will end if the data buffer is not to be looped.

 

 

 

 

 

various sources, and can be cleared by writing a 1 to the

 

 

 

If looping is to occur, DMA transfers will continue

 

 

 

 

 

bit(s) to be cleared.

 

 

 

 

 

 

 

 

 

 

 

from the beginning of the table until the channel is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

turned off.

 

 

 

 

PCI Control Register.

 

 

 

 

 

 

 

 

 

 

6. Bits in the PCI Control/Status register control whether

 

This register must be initialized by the DSP ROM code

 

 

 

an interrupt occurs when the EOL is reached or when

 

prior to PCI enumeration. (It has no effect in ISA or USB

 

 

 

the FLAG bit is set.

 

 

 

mode.) Once the Configuration Ready bit has been set to 1,

 

 

 

 

 

 

 

 

 

 

 

 

the PCI Control Register becomes read-only, and further

 

 

 

 

 

 

 

 

 

 

 

 

access by the DSP to configuration space is disallowed. The

 

 

 

 

 

 

 

 

 

 

 

 

bigs of this register are shown in Table 6 on page 10.

 

 

 

 

Table 5. PCI Interrupt Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Name

 

 

 

Comments

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Reserved

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Rx0 DMA Channel Interrupt

 

Receive Channel 0 Bus Master Transactions

 

 

 

 

 

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Rx1 DMA Channel Interrupt

 

Receive Channel 1 Bus Master Transactions

 

 

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REV. PrA

 

This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

 

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

 

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Page 8 Page 10
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Contents Preliminary Technical Data Words on-chip 16-bit RAM for Data Memory and 16K 48K words of on-chip RAM on P1, configured as 32KREV. PrA Rupts. a 16-bit count register Tcount is decremented Programmable interval timer generates periodic interOutput DSP-DSP Semaphore DSP-DSP Interrupt DSP-DSPADSP-2192 Loop stack interrupt enableADSP-2192 includes a 33MHz, 32 bit bus master PCI Industry standard AC’97 serial interface AC-LinkPliant codecs to the ADSP-2192. The ACLink implements Ification. This interface supports the high data ratesTion. BAR2 is used to access 24-bit DSP memory BAR3 DSP memory accesses use BAR2 or BAR3 of each funcDSP, using the REG instruction BAR3 registers appear in on page 14 and TableMode the functions of the registers are mapped as follows Rpci Dmah controller can be programmed to perform scatADSP-2192 without processor intervention. In scat Tx0 DMA Channel Interrupt Transmit Channel 0 Bus Master TransactionsRthroughHany function. As long as the Memory Space access Target accessesI to registers and DSP memory can goRegister or memory location within the ADSP-2192. Simi BistInta Data Word. BAR3 Mode is typically used for Data MemoryPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Reserved UnusedA15 9FFC 7FFC0x4-0x5 DSP Memory Buffer Size 0x0-0x3 DSP Memory Buffer Base Addr0x6-0x7 DSP Memory Buffer RD Offset 0x8-0x9 DSP Memory Buffer WR OffsetEP6 EP5EP7 EP8Release Number returned in the GET Device Descriptor command is contained in this register.Release Number is 0x0100, which corresponds to Device-specific attributes returned in the GETUSB EP5 NAK USB EP4 NAKUSB EP6 NAK USB EP7 NAKA21 INT = Active interrupt for the 8052 MCU ISE = Current interrupt is for a Setup tokenThisR registerHprovides information as the total size Fixed Endpoints Control Endpoint0x01 0x02 0x00 ADIREV. PrA A23 XXX USB McucodeBRequest 0xA0 USB RegioWValue L AddressWValue H A27 If for some reason the host sends more data than the max Packetsize, theNUSB core accepts it, as long as there isSufficientCroom in theAFIFO Deassertion of PDW1 high causes a wake-up of the DSP Power themselves and the ADSP-2192 completely downAn active lowIRST input to be derived from PCI RST Pmeen output from the Combo Master shouldFifo Interfaces reset the DSP under their control as needed SMSelIBit 3 Stereo / Mono Select AC’97 ModeEslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only Is shown as a no connect in on page 33 theseADSP-2192 can be clocked by a crystal oscillator. If a ADSP-2192 Boot Process FlowForEthis configuration.T Manufacturer.I a parallel-resonant, fundamental frequencyRmicroprocessorH -grade 24.576 MHz crystal should be used Run-time library that includes DSP and mathematical func Tion-level simulator a C/C++ compiler and a C/C++A35 AD1 AD0AD2 AD3130 CBE0 CBE1 CBE2 CBE3 CLKClkrun Devsel Frame GNT Idsel Intab 131 128 PCI / ISA InterruptPAR IrdyPcignd PcivddEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Mode Select Emulator Logic ResetEmulator Data Output Acvaux Aiognd Avdd Ctrlaux Ctrlvdd IgndIvdd Rvaux Rvdd TBD Specifications are subject to changeSupply Current Idle Supply Current Dynamic @ 160 Mips InternalInput Capacitance6 FIN=1 MHz VIN=2.5VAddress Setup to IOR / IOW Falling AEN Setup to IOR / IOW FallingWrite Data Setup to IOW Rising IOR / IOW Strobe Width 100Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
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