Analog Devices ADSP-2192 Transmit Channel 0 Bus Master Transactions, Tx0 DMA Channel Interrupt

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October 2000

 

 

 

 

 

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ADSP-2192

 

For current information contact Analog Devices at (781) 461-3881

 

 

 

 

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Table 5. PCI Interrupt Register (Continued)

 

 

 

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Comments

 

 

Bit

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3

 

 

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Transmit Channel 0 Bus Master Transactions

 

 

Tx0 DMA Channel Interrupt

4

 

 

Tx1 DMA Channel Interrupt

Transmit Channel 1 Bus Master Transactions

 

 

 

 

 

 

 

5

 

 

Incoming Mailbox 0 PCI Interrupt

PCI to DSP Mailbox 0 Transfer

 

 

 

 

 

 

 

 

6

 

 

Incoming Mailbox 1 PCI Interrupt

PCI to DSP Mailbox 1 Transfer

 

 

 

 

 

 

 

 

7

 

 

Outgoing Mailbox 0 PCI Interrupt

DSP to PCI Mailbox 0 Transfer

 

 

 

 

 

 

 

 

8

 

 

Outgoing Mailbox 1 PCI Interrupt

DSP to PCI Mailbox 1 Transfer

 

9Reserved

10Reserved

11

GPIO Wakeup

I/O Pin Initiated

 

 

 

12

AC’97 Wakeup

AC’97 Interface Initiated

 

 

 

13

PCI Master Abort Interrupt

PCI Interface Master Abort Detected

 

 

 

14

PCI Target Abort Interrupt

PCI Interface Target Abort Detected

 

 

 

15

Reserved

 

Table 6. PCI Control Register

Bit

Name

Comments

 

 

 

 

 

 

1-0

PCI Functions

00 = one PCI Function

 

Configured

enabled, 01= two functions,

 

 

10= three functions

 

 

 

2

Configuration

When 0, disables PCI

 

Ready

accesses to the ADSP-2192

 

 

(terminated with Retry).

 

 

Must be set to 1 by DSP

 

 

ROM code after initializing

 

 

configuration space. Once

 

 

1, cannot be written to 0.

 

 

 

15-3

Reserved

 

 

 

 

ADSP-2192 PCI Configuration Space

The ADSP-2192 PCI Interface provides three separate configuration spaces, one for each possible function. This document describes the registers in each function, their reset condition, and how the three functions interact to access and control the ADSP-2192 hardware.

Management. Generally, registers that are unimplemented or read-only in one function are similarly defined in the other functions. Each function contains four base address registers that are used to access ADSP-2192 control regis- ters and DSP memory.

Base address register (BAR) 1 is used to access the ADSP-2192 control registers. Accesses to the control regis- ters via BAR1 uses PCI memory accesses. BAR1 requests a memory allocation of 1024 bytes. Access to DSP memory occurs via BAR2 and BAR3. BAR2 is used to access 24-bit DSP memory (for DSP program downloading) while BAR3 is used to access 16-bit DSP memory. BAR4 provides I/O space access to both the control registers and the DSP memory.

Table 7 on page 11 shows the configuration space headers for the three spaces. While these are the default uses for each of the configurations, they can be redefined to support any possible function by writing to the class code register of that function during boot. Additionally, during boot time, the DSP can disable one or more of the functions. If only two functions are enabled, they will be functions 0 and 1. If only one function is enabled, it will be function 0.

Interactions Between the Three PCI Configurations

Similarities Between the Three PCI Functions

Because the configurations must access and control a single

 

 

Each function contains a complete set of registers in the

set of resources, potential conflicts can occur between the

 

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predefined header region as defined in the PCI Local Bus

control specified by the configuration.

 

 

 

 

 

 

 

 

 

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Specification Revision 2.2. In addition, each function con-

 

 

 

 

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tains the optional registers to support PCI Bus Power

 

 

 

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This information applies to a product under development. Its characteristics and specifications are subject to changePwith-

 

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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Page 9 Page 11
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Page 9 Page 11
Contents Preliminary Technical Data 48K words of on-chip RAM on P1, configured as 32K Words on-chip 16-bit RAM for Data Memory and 16KREV. PrA Programmable interval timer generates periodic inter Rupts. a 16-bit count register Tcount is decrementedDSP-DSP Output DSP-DSP Semaphore DSP-DSP InterruptLoop stack interrupt enable ADSP-2192Pliant codecs to the ADSP-2192. The ACLink implements Industry standard AC’97 serial interface AC-LinkADSP-2192 includes a 33MHz, 32 bit bus master PCI Ification. This interface supports the high data ratesDSP, using the REG instruction DSP memory accesses use BAR2 or BAR3 of each funcTion. BAR2 is used to access 24-bit DSP memory BAR3 BAR3 registers appear in on page 14 and TableRpci Dmah controller can be programmed to perform scat Mode the functions of the registers are mapped as followsADSP-2192 without processor intervention. In scat Transmit Channel 0 Bus Master Transactions Tx0 DMA Channel InterruptRegister or memory location within the ADSP-2192. Simi Target accessesI to registers and DSP memory can goRthroughHany function. As long as the Memory Space access BistData Word. BAR3 Mode is typically used for Data Memory IntaPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Unused ReservedA15 7FFC 9FFC0x6-0x7 DSP Memory Buffer RD Offset 0x0-0x3 DSP Memory Buffer Base Addr0x4-0x5 DSP Memory Buffer Size 0x8-0x9 DSP Memory Buffer WR OffsetEP7 EP5EP6 EP8Release Number is 0x0100, which corresponds to Descriptor command is contained in this register.Release Number returned in the GET Device Device-specific attributes returned in the GETUSB EP6 NAK USB EP4 NAKUSB EP5 NAK USB EP7 NAKA21 ThisR registerHprovides information as the total size ISE = Current interrupt is for a Setup tokenINT = Active interrupt for the 8052 MCU Fixed Endpoints Control EndpointADI 0x01 0x02 0x00REV. PrA A23 USB Mcucode XXXWValue L USB RegioBRequest 0xA0 AddressWValue H A27 Packetsize, theNUSB core accepts it, as long as there is If for some reason the host sends more data than the maxSufficientCroom in theAFIFO An active lowIRST input to be derived from PCI RST Power themselves and the ADSP-2192 completely downDeassertion of PDW1 high causes a wake-up of the DSP Pmeen output from the Combo Master shouldFifo Eslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only SMSelIBit 3 Stereo / Mono Select AC’97 ModeInterfaces reset the DSP under their control as needed Is shown as a no connect in on page 33 theseADSP-2192 Boot Process Flow ADSP-2192 can be clocked by a crystal oscillator. If aManufacturer.I a parallel-resonant, fundamental frequency ForEthis configuration.TRmicroprocessorH -grade 24.576 MHz crystal should be used Tion-level simulator a C/C++ compiler and a C/C++ Run-time library that includes DSP and mathematical funcA35 AD2 AD0AD1 AD3Clkrun Devsel Frame GNT Idsel Intab CBE0 CBE1 CBE2 CBE3 CLK130 131 128 PCI / ISA InterruptPcignd IrdyPAR PcivddEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Logic Reset Emulator Mode SelectEmulator Data Output Ctrlaux Ctrlvdd Ignd Acvaux Aiognd AvddIvdd Rvaux Rvdd Specifications are subject to change TBDInput Capacitance6 FIN=1 MHz Supply Current Dynamic @ 160 Mips InternalSupply Current Idle VIN=2.5VWrite Data Setup to IOW Rising AEN Setup to IOR / IOW FallingAddress Setup to IOR / IOW Falling IOR / IOW Strobe Width 100Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
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