Analog Devices ADSP-2192 specifications A35

Page 35

 

 

 

 

 

 

 

Y

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

For current information contact Analog Devices at (781) 461-3881

 

ADSP-2192

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

October 2000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The JTAG signals are terminated on the emulator probe

 

 

nector (a 2 Irow × 7 pin strip header) such as that shown in

 

E

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

as follows:

 

 

 

 

 

 

 

 

 

 

 

 

RFigureH10 on page 35. The emulator probe plugs directly

 

 

 

 

 

 

 

 

 

 

 

 

P

 

C

 

 

 

A

for chip-on-board emulation. You must

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ontoE this connectorT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 27. Analog Devices DSP Emulator Probe

 

 

 

 

 

add thisDconnector to your target board design if you intend

 

 

 

 

 

to use the ADSP-2192 emulator. The total trace length

Terminations

 

 

 

 

 

 

 

 

 

 

 

between the emulator connector and the furthest device

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal

Termination

 

 

 

 

 

 

 

 

 

 

 

sharing the emulation JTAG pins should be limited to 15

 

 

 

 

 

 

 

 

 

 

 

 

inches maximum for guaranteed operation. This length

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS

Driven through 22 Ω Resistor (16 mA

 

 

 

 

 

restriction must include emulation JTAG signals which are

 

 

 

 

 

 

 

 

 

 

Driver)

 

 

 

 

 

 

 

 

 

 

 

routed to one or more ADSP-2192 devices, or a combina-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tion of ADSP-2192 devices and other JTAG devices on the

 

TCK

Driven at 10 MHz through 22 Ω

 

Resistor

 

 

 

chain.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(16 mA Driver)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The 14-pin, 2-row pin strip header is keyed at the pin 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Active Low Driven through 22 Ω

 

Resistor

 

 

 

location; pin 3 must be removed from the header. The pins

 

TRST

 

 

 

 

 

 

 

 

 

(16 mA Driver) (Pulled Up by On-Chip

 

 

 

 

must be 0.025 inch square and at least 0.20 inch in length.

 

 

 

 

 

 

 

 

 

 

 

 

20 kΩ Resistor);

 

is driven low until

 

 

 

Pin spacing should be 0.1 × 0.1 inches. Pin strip headers

 

 

 

 

TRST

 

 

 

 

 

 

 

the emulator probe is turned on by the

 

 

 

 

are available from vendors such as 3M, McKenzie and

 

 

 

 

 

 

 

 

 

 

 

 

emulator at software start-up. After software

 

 

 

Samtec.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

start-up,

TRST

is driven high.

 

 

 

 

 

 

 

 

The BTMS, BTCK, BTRST and BTDI signals are pro-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

vided so the test access port can also be used for board-level

 

TDI

Driven by 22 Ω Resistor (16 mA Driver)

 

 

 

 

testing. When the connector is not being used for emula-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

One TTL Load, Split (160/220)

 

 

 

 

 

 

 

 

tion, place jumpers between the Bxxx pins and the xxx pins.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

If the test access port will not be used for board testing, tie

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKIN

One TTL Load, Split (160/220)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BTRST and BTCK pins to GND. The TRST pin must be

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

asserted after power-up (through

 

 

 

 

on the connec-

 

 

 

 

 

 

 

Ω

 

 

 

 

 

 

 

 

 

BTRST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMU

 

 

 

 

 

 

 

 

 

 

 

 

tor) or held low for proper operation of the ADSP-2192.

 

Active Low 4.7 k Pull-Up Resistor, One

 

 

 

 

 

 

 

TTL Load (Open-Drain Output from the

 

 

 

None of the Bxxx pins (Pins 5, 7, 9, 11) are connected on

 

 

 

 

DSP)

 

 

 

 

 

 

 

 

 

 

 

the emulator probe.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 11 on page 36 shows JTAG scan path connections

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

for systems that contain multiple ADSP-2192 processors

 

 

 

 

 

 

 

 

1

 

 

2

 

 

 

 

 

 

 

 

 

To make it easier to evaluate the ADSP-219x DSP family

 

 

 

 

 

 

 

GN D

 

 

 

 

 

 

 

 

 

 

E M U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

4

 

 

 

 

 

 

 

 

 

for your application, Analog Devices sells the ADSP-2192

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EZ-KIT Lite™. The ADSP-2192 EZ-KIT Lite provides

 

 

 

 

KE Y (NO PIN )

 

 

 

 

 

 

 

 

 

 

CLKIN (OP TIO NAL)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

6

 

 

 

 

 

 

 

 

 

developers with a cost-effective method for evaluating of the

 

 

 

 

 

 

 

BTM S

 

 

 

 

 

 

 

 

 

 

TM S

ADSP-219x family of DSPs. The EZ-KIT Lite includes an

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

8

 

 

 

 

 

 

 

 

 

ADSP-2192 DSP evaluation board and fundamental

 

 

 

 

 

 

 

 

 

BTC K

 

 

 

 

 

 

 

 

 

 

TCK

debugging software. The evaluation board in this kit con-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

10

 

 

 

 

 

 

 

 

 

tains an ADSP-2192 digital signal processor, Flash

 

 

 

 

 

 

 

 

 

 

BTRS T

 

 

 

 

9

 

 

 

 

 

TRST

Memory, Audio/Telephony type Codec, breadboard area,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

12

 

 

 

 

 

 

 

 

 

Flag LED, Reset/Interrupt/Flag push buttons, and

 

 

 

 

 

 

 

 

 

 

BTDI

 

 

 

 

 

 

 

 

 

 

TDI

ADSP-2192 peripheral port connectors. The peripheral

 

 

 

 

 

 

 

 

13

 

 

14

 

 

 

 

 

 

 

 

 

connectors include a JTAG test and emulation port connec-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tor that supports the Analog Devices emulators and other

 

 

 

 

 

 

 

GN D

 

 

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TOP VIEW

connector locations that provide additional evaluation and

 

 

 

 

 

 

 

 

 

 

interface points to the ADSP-2192 peripheral ports. The

 

 

Figure 10. Target Board Connector For ADSP-2192

ADSP-2192 EZ-KIT Lite comes with an evaluation suite of

 

 

the VisualDSP++ integrated development environment

 

 

Analog Devices Emulator (Jumpers in Place)

 

 

with the C/C++ compiler, assembler, and linker that sup-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ports typical debug functions including memory/register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

read and write, halt, run, and single step. All software tools

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

are limited to use with the EZ-KIT Lite product.

 

 

Y

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

H

 

 

 

 

 

REV. PrA

 

 

 

This information applies to a product under development. Its characteristics and specifications are subjectPto change with-

 

A35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed toEin writing.

 

T

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

 

 

 

Page 34 Page 36
Image 35
Page 34 Page 36
Contents Preliminary Technical Data Words on-chip 16-bit RAM for Data Memory and 16K 48K words of on-chip RAM on P1, configured as 32KREV. PrA Rupts. a 16-bit count register Tcount is decremented Programmable interval timer generates periodic interOutput DSP-DSP Semaphore DSP-DSP Interrupt DSP-DSPADSP-2192 Loop stack interrupt enableIfication. This interface supports the high data rates Industry standard AC’97 serial interface AC-LinkADSP-2192 includes a 33MHz, 32 bit bus master PCI Pliant codecs to the ADSP-2192. The ACLink implementsBAR3 registers appear in on page 14 and Table DSP memory accesses use BAR2 or BAR3 of each funcTion. BAR2 is used to access 24-bit DSP memory BAR3 DSP, using the REG instructionADSP-2192 without processor intervention. In scat Mode the functions of the registers are mapped as followsRpci Dmah controller can be programmed to perform scat Tx0 DMA Channel Interrupt Transmit Channel 0 Bus Master TransactionsBist Target accessesI to registers and DSP memory can goRthroughHany function. As long as the Memory Space access Register or memory location within the ADSP-2192. SimiInta Data Word. BAR3 Mode is typically used for Data MemoryPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Reserved UnusedA15 9FFC 7FFC0x8-0x9 DSP Memory Buffer WR Offset 0x0-0x3 DSP Memory Buffer Base Addr0x4-0x5 DSP Memory Buffer Size 0x6-0x7 DSP Memory Buffer RD OffsetEP8 EP5EP6 EP7Device-specific attributes returned in the GET Descriptor command is contained in this register.Release Number returned in the GET Device Release Number is 0x0100, which corresponds toUSB EP7 NAK USB EP4 NAKUSB EP5 NAK USB EP6 NAKA21 Fixed Endpoints Control Endpoint ISE = Current interrupt is for a Setup tokenINT = Active interrupt for the 8052 MCU ThisR registerHprovides information as the total sizeREV. PrA A23 0x01 0x02 0x00ADI XXX USB McucodeAddress USB RegioBRequest 0xA0 WValue LWValue H A27 SufficientCroom in theAFIFO If for some reason the host sends more data than the maxPacketsize, theNUSB core accepts it, as long as there is Pmeen output from the Combo Master should Power themselves and the ADSP-2192 completely downDeassertion of PDW1 high causes a wake-up of the DSP An active lowIRST input to be derived from PCI RSTFifo Is shown as a no connect in on page 33 these SMSelIBit 3 Stereo / Mono Select AC’97 ModeInterfaces reset the DSP under their control as needed Eslot Bits 7-4 AC’97 Slot Select AC’97 Mode OnlyADSP-2192 can be clocked by a crystal oscillator. If a ADSP-2192 Boot Process FlowRmicroprocessorH -grade 24.576 MHz crystal should be used ForEthis configuration.TManufacturer.I a parallel-resonant, fundamental frequency Run-time library that includes DSP and mathematical func Tion-level simulator a C/C++ compiler and a C/C++A35 AD3 AD0AD1 AD2131 128 PCI / ISA Interrupt CBE0 CBE1 CBE2 CBE3 CLK130 Clkrun Devsel Frame GNT Idsel IntabPcivdd IrdyPAR PcigndEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Data Output Emulator Mode SelectEmulator Logic Reset Ivdd Rvaux Rvdd Acvaux Aiognd AvddCtrlaux Ctrlvdd Ignd TBD Specifications are subject to changeVIN=2.5V Supply Current Dynamic @ 160 Mips InternalSupply Current Idle Input Capacitance6 FIN=1 MHzIOR / IOW Strobe Width 100 AEN Setup to IOR / IOW FallingAddress Setup to IOR / IOW Falling Write Data Setup to IOW RisingSub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
Top Page Image Contents