Analog Devices ADSP-2192 specifications 48K words of on-chip RAM on P1, configured as 32K

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October 2000

 

 

 

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ADSP-2192

 

For current information contact Analog Devices at (781) 461-3881

 

 

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• 48K words of on-chip RAM on P1, configured as 32K

ADSP-219X DSP CORE FEATURES (CONTINUED)

 

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words on-chip 16-bit RAM for Data Memory and 16K

•RSingleH-Cycle Context Switch Between Two Sets of

 

 

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words on-chip 24-bit RAM for Program Memory

 

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ComputationalTand DAG Registers

 

 

 

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• 4K words of additional on-chip RAM shared by both

• ParallelDExecution of Computation and Memory

Instructions

cores, configured as 4K words on-chip 16-bit RAM

 

•Pipelined Architecture Supports Efficient Code Execu- tion at Speeds up to 160 MIPS

•Register File Computations with All Non-conditional, Non-parallel Computational Instructions

•Powerful Program Sequencer Provides Zero- Overhead Looping and Conditional Instruction Execution

•Architectural Enhancements for Compiled C/C++ Code Efficiency

•Architecture Enhancements Beyond ADSP-218x Fam- ily are Supported with Instruction Set Extensions for Added Registers, Ports, and Peripherals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I N T ER RU PT CO NT R O LL ER /

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TI M ER/ F LA G S

 

 

 

 

 

A D S P - 2 1 9 x

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DS P C OR E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C A C H E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64 x 2 4 - BI T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D AG 1

 

 

 

D A G 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PR O G R A M

 

 

 

 

 

 

 

 

 

 

 

 

 

4 x 4 x1 6

 

 

 

4x 4 x 1 6

 

 

 

 

 

 

SEQ U ENC E R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PM AD D RESS BU S

 

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DM AD D R ESS BU S

 

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PM D A T A B U S

 

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B U S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C ON N E CT

 

 

DM DA T A BU S

 

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( PX)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D AT A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C O R E

 

 

 

 

 

R EG I ST ER

 

 

 

 

 

 

 

 

 

 

 

 

 

IN T ERF A C E

 

 

 

 

 

FI L E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I N PU T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R EG I ST ERS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESUL T

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R EG I ST ERS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M U L T

 

 

 

 

 

 

 

B A RR EL

 

 

 

AL U

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16 x 16 -B I T

 

 

 

SHI F T ER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2. ADSP-219x DSP Core

ADSP-2192 DSP FEATURES (CONTINUED)

•Flexible power management with selectable power-down and idle modes

•Programmable PLL supports frequency multiplication, enabling full-speed operation from low-speed input clocks

•2.5V internal operation supports 3.3V/5.0V compliant I/O

•A Host port that supports either PCI (PCI interface and CardBus) or USB (USB 1.1 compliant) interfaces; both with DMA capability

•Sub-ISA Interface

•An AC’97 port supporting AC’97 Revision 2.1 compli- ant interface for External Audio, Modem, and Handset Codecs with DMA capability

•Eight dedicated general-purpose I/O pins with inte- grated interrupt support

•Each DSP core has a programmable 32-bit interval timer

•Five DMA channels available on each core

•Boot methods include booting through PCI port, USB port, or serial EEPROM

•JTAG Test Access Port supports on-chip emulation and system debugging

•144-lead LQFP package (20x20x1.4mm)

General note

This data sheet provides preliminary information for the ADSP-2192 Digital Signal Processor.

GENERAL DESCRIPTION

The ADSP-2192 is a single-chip microcomputer optimized for digital signal processing (DSP) and other high speed numeric processing applications.

The ADSP-2192 combines the ADSP-219x family base architecture (three computational units, two data address generators and a program sequencer) into a chip with two core processors. The ADSP-2192 includes a PCI-compati- ble port, a USB-compatible port, an AC’97-compatible port, a DMA controller, a programmable timer, general purpose Programmable Flag pins, extensive interrupt capa- bilities, and on-chip program and data memory spaces.

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Two ADSP-219x core processors (P0 and P1) on each

The ADSP-2192 architecture is code compatible with

 

 

 

ADSP-2192 DSP chip

 

 

 

ADSP-218x family DSPs. Though the architectures are

 

 

 

80K words of on-chip RAM on P0, configured as 64K

 

 

 

compatible, the ADSP-2192 architecture has many

 

 

 

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words on-chip 16-bit RAM for Data Memory and 16K

enhancements over the ADSP-218x architecture. The

 

 

 

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words on-chip 24-bit RAM for Program Memory

 

 

 

 

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This information applies to a product under development. Its characteristics and specifications are subject to changePwith-

 

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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Contents Preliminary Technical Data 48K words of on-chip RAM on P1, configured as 32K Words on-chip 16-bit RAM for Data Memory and 16KREV. PrA Programmable interval timer generates periodic inter Rupts. a 16-bit count register Tcount is decrementedDSP-DSP Output DSP-DSP Semaphore DSP-DSP InterruptLoop stack interrupt enable ADSP-2192Pliant codecs to the ADSP-2192. The ACLink implements Industry standard AC’97 serial interface AC-LinkADSP-2192 includes a 33MHz, 32 bit bus master PCI Ification. This interface supports the high data ratesDSP, using the REG instruction DSP memory accesses use BAR2 or BAR3 of each funcTion. BAR2 is used to access 24-bit DSP memory BAR3 BAR3 registers appear in on page 14 and TableADSP-2192 without processor intervention. In scat Mode the functions of the registers are mapped as followsRpci Dmah controller can be programmed to perform scat Transmit Channel 0 Bus Master Transactions Tx0 DMA Channel InterruptRegister or memory location within the ADSP-2192. Simi Target accessesI to registers and DSP memory can goRthroughHany function. As long as the Memory Space access BistData Word. BAR3 Mode is typically used for Data Memory IntaPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Unused ReservedA15 7FFC 9FFC0x6-0x7 DSP Memory Buffer RD Offset 0x0-0x3 DSP Memory Buffer Base Addr0x4-0x5 DSP Memory Buffer Size 0x8-0x9 DSP Memory Buffer WR OffsetEP7 EP5EP6 EP8Release Number is 0x0100, which corresponds to Descriptor command is contained in this register.Release Number returned in the GET Device Device-specific attributes returned in the GETUSB EP6 NAK USB EP4 NAKUSB EP5 NAK USB EP7 NAKA21 ThisR registerHprovides information as the total size ISE = Current interrupt is for a Setup tokenINT = Active interrupt for the 8052 MCU Fixed Endpoints Control EndpointREV. PrA A23 0x01 0x02 0x00ADI USB Mcucode XXXWValue L USB RegioBRequest 0xA0 AddressWValue H A27 SufficientCroom in theAFIFO If for some reason the host sends more data than the maxPacketsize, theNUSB core accepts it, as long as there is An active lowIRST input to be derived from PCI RST Power themselves and the ADSP-2192 completely downDeassertion of PDW1 high causes a wake-up of the DSP Pmeen output from the Combo Master shouldFifo Eslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only SMSelIBit 3 Stereo / Mono Select AC’97 ModeInterfaces reset the DSP under their control as needed Is shown as a no connect in on page 33 theseADSP-2192 Boot Process Flow ADSP-2192 can be clocked by a crystal oscillator. If aRmicroprocessorH -grade 24.576 MHz crystal should be used ForEthis configuration.TManufacturer.I a parallel-resonant, fundamental frequency Tion-level simulator a C/C++ compiler and a C/C++ Run-time library that includes DSP and mathematical funcA35 AD2 AD0AD1 AD3Clkrun Devsel Frame GNT Idsel Intab CBE0 CBE1 CBE2 CBE3 CLK130 131 128 PCI / ISA InterruptPcignd IrdyPAR PcivddEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Data Output Emulator Mode SelectEmulator Logic Reset Ivdd Rvaux Rvdd Acvaux Aiognd AvddCtrlaux Ctrlvdd Ignd Specifications are subject to change TBDInput Capacitance6 FIN=1 MHz Supply Current Dynamic @ 160 Mips InternalSupply Current Idle VIN=2.5VWrite Data Setup to IOW Rising AEN Setup to IOR / IOW FallingAddress Setup to IOR / IOW Falling IOR / IOW Strobe Width 100Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
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