Analog Devices ADSP-2192 specifications WValue H

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ADSP-2192

 

 

For current information contact Analog Devices at (781) 461-3881

 

 

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Table 20. USB REGIO (Register Read) (Continued)

 

 

 

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Description

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Address <8:15>

 

 

 

 

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wLength (L)

 

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Length = 02 bytes

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October 2000

Since there are three possible interfaces supported, each interface has its own DSP download address and uses its own BULK pipe to download code. The driver for each interface must set the download address before beginning to use the BULK pipe to download DSP code. The down- load address will auto-increment as each byte of data is sent on the BULK pipe to the DSP.

DSP instructions are three bytes long, and USB BULK pipes have even-number packet sizes. The instructions to be downloaded must be formatted into four-byte groups with the least significant byte always zero. The USB interface strips off the least significant byte and formats the DSP instruction properly before writing it into the program memory. For example, to write the three-byte opcode 0x400000 to DSP program memory, the driver sends 0x40000000 down the BULK pipe.

The following example illustrates the proper order of com- mands and synchronizing that the driver must follow.

1.Device enumerates with two interfaces. Each interface has the capability to download DSP code and can ini- tiate at any time.

2.The driver for interface 1 begins code download by sending the USB REGIO (Write) command with the starting download address.

The driver must wait for this command to finish before starting code download.

3.The driver for interface 2 begins code download by sending the USB REGIO (Write) command with the starting download address.

The driver must wait for this command to finish before starting code download.

General Comments:

•DSP code download is only available after the ADSP-2192 has re-enumerated using the MCU soft firmware. The DSP code download command will not be available in the MCU boot ROM for the default CONFIG device.

•After setting the download addresses using the USB REGIO (Write) command, code download can be ini- tiated for any length using normal BULK traffic.

Example Initialization Process

After attachment to the USB bus, the ADSP-2192 identifies itself as a CONFIG device with one endpoint(s), which refers to its one control, EP0. This will cause a generic user-defined CONFIG driver to load.

The CONFIG driver downloads appropriate MCU code to setup the MCU, which includes the specific device descrip- tors, interfaces, and endpoints.

The external Serial EEPROM is read by the DSP and trans- ferred to the MCU. The CONFIG driver through the control EP0 pipe generates a register read to determine the configuration value. Based on this configuration code, the host downloads the proper USB configurations to the MCU.

Finally the driver writes the USB Control Register, causing the device to disconnect and then reconnect so the new downloaded configuration is enumerated by the system. Upon enumeration, each interface loads the appropriate device driver.

An example of this procedure is configuring the ADSP-2192 to be an ADSL modem and a FAX modem.

4. Each driver now streams the code to be downloaded to

1. ADSP-2192 device is attached to USB bus. System

 

 

 

 

the DSP: driver 1 onto BULK EP1 for interface 1, and

 

enumerates the CONFIG device in the ADSP-2192

 

 

 

driver 2 onto BULK EP2 for interface 2. The code is

 

first. A user-defined driver is loaded.

 

 

 

 

 

 

 

 

written to the DSP in 3-byte instructions starting at the

2.

The user-defined driver reads the device descriptor,

 

 

 

 

location specified by the USB REGIO (Write) com-

 

 

 

 

 

which identifies the card as an ADSL/FAX modem.

 

 

 

 

mand. The driver must wait for each command to

 

 

 

 

 

3.

The user-defined driver downloads USB configuration

 

 

 

finish before sending a new code download address.

 

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and MCU code to the MCU for interface 1, which is

 

 

 

 

 

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If there is more code to be downloaded at a different

 

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the ADSL modem.

 

 

 

 

 

 

 

 

 

 

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starting address, the driver begins the entire sequence

 

 

 

 

 

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again, using steps 1-4.

 

 

 

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This information applies to a product under development. Its characteristics and specifications are subject to changePwith-

 

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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Contents Preliminary Technical Data 48K words of on-chip RAM on P1, configured as 32K Words on-chip 16-bit RAM for Data Memory and 16KREV. PrA Programmable interval timer generates periodic inter Rupts. a 16-bit count register Tcount is decrementedDSP-DSP Output DSP-DSP Semaphore DSP-DSP InterruptLoop stack interrupt enable ADSP-2192Pliant codecs to the ADSP-2192. The ACLink implements Industry standard AC’97 serial interface AC-LinkADSP-2192 includes a 33MHz, 32 bit bus master PCI Ification. This interface supports the high data ratesDSP, using the REG instruction DSP memory accesses use BAR2 or BAR3 of each funcTion. BAR2 is used to access 24-bit DSP memory BAR3 BAR3 registers appear in on page 14 and TableADSP-2192 without processor intervention. In scat Mode the functions of the registers are mapped as followsRpci Dmah controller can be programmed to perform scat Transmit Channel 0 Bus Master Transactions Tx0 DMA Channel InterruptRegister or memory location within the ADSP-2192. Simi Target accessesI to registers and DSP memory can goRthroughHany function. As long as the Memory Space access BistData Word. BAR3 Mode is typically used for Data Memory IntaPCI Dword BYTE3 BYTE2 BYTE1 BYTE0 Unused ReservedA15 7FFC 9FFC0x6-0x7 DSP Memory Buffer RD Offset 0x0-0x3 DSP Memory Buffer Base Addr0x4-0x5 DSP Memory Buffer Size 0x8-0x9 DSP Memory Buffer WR OffsetEP7 EP5EP6 EP8Release Number is 0x0100, which corresponds to Descriptor command is contained in this register.Release Number returned in the GET Device Device-specific attributes returned in the GETUSB EP6 NAK USB EP4 NAKUSB EP5 NAK USB EP7 NAKA21 ThisR registerHprovides information as the total size ISE = Current interrupt is for a Setup tokenINT = Active interrupt for the 8052 MCU Fixed Endpoints Control EndpointREV. PrA A23 0x01 0x02 0x00ADI USB Mcucode XXXWValue L USB RegioBRequest 0xA0 AddressWValue H A27 SufficientCroom in theAFIFO If for some reason the host sends more data than the maxPacketsize, theNUSB core accepts it, as long as there is An active lowIRST input to be derived from PCI RST Power themselves and the ADSP-2192 completely downDeassertion of PDW1 high causes a wake-up of the DSP Pmeen output from the Combo Master shouldFifo Eslot Bits 7-4 AC’97 Slot Select AC’97 Mode Only SMSelIBit 3 Stereo / Mono Select AC’97 ModeInterfaces reset the DSP under their control as needed Is shown as a no connect in on page 33 theseADSP-2192 Boot Process Flow ADSP-2192 can be clocked by a crystal oscillator. If aRmicroprocessorH -grade 24.576 MHz crystal should be used ForEthis configuration.TManufacturer.I a parallel-resonant, fundamental frequency Tion-level simulator a C/C++ compiler and a C/C++ Run-time library that includes DSP and mathematical funcA35 AD2 AD0AD1 AD3Clkrun Devsel Frame GNT Idsel Intab CBE0 CBE1 CBE2 CBE3 CLK130 131 128 PCI / ISA InterruptPcignd IrdyPAR PcivddEmulator Event Pin Emulator Clock Input Emulator Data Input Emulator Data Output Emulator Mode SelectEmulator Logic Reset Ivdd Rvaux Rvdd Acvaux Aiognd AvddCtrlaux Ctrlvdd Ignd Specifications are subject to change TBDInput Capacitance6 FIN=1 MHz Supply Current Dynamic @ 160 Mips InternalSupply Current Idle VIN=2.5VWrite Data Setup to IOW Rising AEN Setup to IOR / IOW FallingAddress Setup to IOR / IOW Falling IOR / IOW Strobe Width 100Sub-ISA Interface Write Cycle Timing Diagram TBD C/W REV. PrA A47 CREV. PrA a A49 Ordering Guide

ADSP-2192 specifications

The Analog Devices ADSP-2192 is a high-performance digital signal processor (DSP) that stands out in the realm of signal processing applications. The device is part of the ADSP-2100 family, which has been recognized for its ability to deliver high-speed computations and efficient processing capabilities. The ADSP-2192 is particularly well-suited for applications requiring advanced digital signal processing, such as telecommunications, audio processing, and industrial control systems.

One of the key features of the ADSP-2192 is its dual-core architecture. This allows for parallel processing capabilities, enabling the device to handle multiple tasks simultaneously. Each core can execute instructions independently, which significantly boosts the overall processing power. The device is built on a 16-bit architecture, supporting 16-bit fixed-point and 40-bit floating-point operations, allowing for a wide range of precision in calculations.

The ADSP-2192 also incorporates a sophisticated instruction set designed for efficient performance. It includes specialized instructions tailored for common signal processing tasks, such as filtering and Fourier transforms. This optimized instruction set enhances the speed and efficiency of data manipulation and computation, making it an ideal choice for real-time applications.

In terms of memory, the ADSP-2192 is equipped with 1 KB of on-chip program memory and 2 KB of data memory. This provides sufficient storage for handling complex algorithms without the need for external memory, reducing latency and increasing processing speed. The device also supports external memory interfaces, enabling developers to expand the system's memory capacity if needed.

Another standout feature of the ADSP-2192 is its rich set of communication interfaces. It supports a variety of communication protocols, including SPI, USART, and I2C, facilitating seamless integration with other devices and systems. This versatility makes it suitable for a wide range of applications, from consumer electronics to industrial automation.

In terms of power consumption, the ADSP-2192 is designed to be energy-efficient, making it an excellent choice for battery-operated devices and applications requiring low power usage. The device operates at a voltage range of 3V to 5V, making it compatible with various power supply systems.

Overall, the Analog Devices ADSP-2192 combines powerful processing capabilities with efficient resource management and versatility, making it a strong contender in the DSP market. Its dual-core architecture, robust instruction set, communication flexibility, and energy-efficient design position it as an essential component for advanced signal processing applications across multiple industries.
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