Samsung M391B5773DH0, M391B5273DH0 specifications VIH.DQDC90

Page 13

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

[ Table 3 ] Single Ended AC and DC input levels for DQ and DM

Symbol

Parameter

DDR3-800/1066

DDR3-1333/1600

Unit

NOTE

Min.

Max.

Min.

Max.

 

 

 

 

 

 

 

1.35V

 

 

 

 

VIH.DQ(DC90)

DC input logic high

VREF + 90

VDD

VREF + 90

VDD

mV

1,5a)

VIL.DQ(DC90)

DC input logic low

VSS

VREF - 90

VSS

VREF - 90

mV

1,6a)

VIH.DQ(AC160)

AC input logic high

VREF + 160

Note 2

-

-

mV

1,2

VIL.DQ(AC160)

AC input logic low

Note 2

VREF - 160

-

-

mV

1,2

VIH.DQ(AC135)

AC input logic high

VREF + 135

Note 2

VREF + 135

Note 2

mV

1,2

VIL.DQ(AC135)

AC input logic low

Note 2

VREF - 135

Note 2

VREF - 135

mV

1,2

VREFDQ(DC)

Reference Voltage for DQ,

0.49*VDD

0.51*VDD

0.49*VDD

0.51*VDD

V

3,4

DM inputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.5V

 

 

 

 

VIH.DQ(DC100)

DC input logic high

VREF + 100

VDD

VREF + 100

VDD

mV

1,5b)

VIL.DQ(DC100)

DC input logic low

VSS

VREF - 100

VSS

VREF - 100

mV

1,6b)

VIH.DQ(AC175)

AC input logic high

VREF + 175

NOTE 2

-

-

mV

1,2,7

VIL.DQ(AC175)

AC input logic low

NOTE 2

VREF - 175

-

-

mV

1,2,8

VIH.DQ(AC150)

AC input logic high

VREF + 150

NOTE 2

VREF + 150

NOTE 2

mV

1,2,7

VIL.DQ(AC150)

AC input logic low

NOTE 2

VREF - 150

NOTE 2

VREF - 150

mV

1,2,8

VREFDQ(DC)

Reference Voltage for DQ,

0.49*VDD

0.51*VDD

0.49*VDD

0.51*VDD

V

3,4

DM inputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE :

1.For input only pins except RESET, VREF = VREFDQ(DC)

2.See ’Overshoot/Undershoot Specification’ on page 18.

3.The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

4.For reference : approx. VDD/2 ± 15mV

5.VIH(dc) is used as a simplified symbol for VIH.CA(a) 1.35V : DC90, b) 1.5V : DC100)

6.VIL(dc) is used as a simplified symbol for VIL.CA(a) 1.35V : DC90, b) 1.5V : DC100)

7.VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150) ; VIH.DQ(AC175) value is used when VREF + 175mV is referenced, VIH.DQ(AC150) value is used when VREF + 150mV is referenced.

8.VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150) ; VIL.DQ(AC175) value is used when VREF - 175mV is referenced, VIL.DQ(AC150) value is used when VREF - 150mV is referenced.

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Contents
Datasheet History Draft Date RevTable Of Contents Address Configuration Key FeaturesDDR3L Unbuffered Dimm Ordering Information Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UnitPin Front Back X72 Dimm Pin Configurations Front side/Back sideSPD and Thermal Sensor for ECC UDIMMs Pin DescriptionPin Name Description Input/Output Functional Description Symbol Type FunctionDram Pin Wiring Mirroring Address Mirroring FeatureConnector Pin Dram Pin Rank SCL SDA Event SA0 SA1 SA2 Function Block DiagramD14 Absolute Maximum Ratings Dram Component Operating Temperature RangeAC & DC Operating Conditions Absolute Maximum DC RatingsAC & DC Input Measurement Levels 11.1 AC & DC Logic Input Levels for Single-ended SignalsVIH.DQDC90 Illustration of Vrefdc tolerance and Vref ac-noise limits Vref TolerancesDifferential Signals Definition AC and DC Logic Input Levels for Differential Signals35V TBD Time Single-ended Requirements for Differential SignalsCK, DQS Vsel Differential Input Cross Point VoltageSlew rate definition for Differential Input Signals Slew Rate Definition for Single Ended Input SignalsAC & DC Output Measurement Levels Single Ended AC and DC Output LevelsSRQse Single-ended Output Slew RateDifferential output slew rate definition Differential Output Slew RateSymbol Description IDD specification definitionDatasheet IDD Spec Table DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 UnitM391B5773DH0 2GB256Mx72 Module M391B5273DH0 4GB512Mx72 ModuleCZQ Input/Output CapacitanceRefresh Parameters by Device Density Electrical Characteristics and AC timingDDR3-1066 Speed Bins DDR3-1600 Speed Bins CL-nRCD-nRP Speed Bin Table NotesDatasheet Timing Parameters by Speed Bin Timing Parameters by Speed GradeMIN MAX Reset Timing Jitter Notes ZQCorrection TSens x Tdriftrate + VSens x Vdriftrate Timing Parameter Notes18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH0 Physical Dimensions18.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0
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