Samsung M391B5273DH0, M391B5773DH0 Differential Input Cross Point Voltage, CK, DQS Vsel

Page 18

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

11.3.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the mid level between of VDD and VSS.

VDD

VIX

VIX

VSEH

CK, DQS

VDD/2

VIX

CK, DQS

VSEL

VSS

Figure 5. VIX Definition

[ Table 7 ] Cross point voltage for differential input signals (CK, DQS) : 1.35V

Symbol

Parameter

DDR3L-800/1066/1333/1600

Unit

NOTE

Min

Max

 

 

 

 

 

 

 

VIX

Differential Input Cross Point Voltage relative to VDD/2 for CK,CK

 

-150

150

mV

1

VIX

Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS

-150

150

mV

 

NOTE :

1.The relationbetween Vix Min/Max and VSEL/VSEH should satisfy following. (VDD/2) + Vix(Min) - VSEL 25mV

VSEH - ((VDD/2) + Vix(Max)) 25mV

[ Table 8 ] Cross point voltage for differential input signals (CK, DQS) : 1.5V

Symbol

Parameter

DDR3-800/1066/1333/1600

Unit

NOTE

Min

Max

 

 

 

 

 

 

 

VIX

 

 

 

 

-150

150

mV

 

Differential Input Cross Point Voltage relative to VDD/2 for CK,CK

 

-175

175

mV

1

 

 

 

 

 

VIX

Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS

-150

150

mV

 

NOTE :

1.Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2 ±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.

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Image 18 Contents
Datasheet Rev History Draft DateTable Of Contents DDR3L Unbuffered Dimm Ordering Information Key FeaturesAddress Configuration Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UnitX72 Dimm Pin Configurations Front side/Back side Pin Front BackPin Description SPD and Thermal Sensor for ECC UDIMMsPin Name Description Symbol Type Function Input/Output Functional DescriptionAddress Mirroring Feature Dram Pin Wiring MirroringConnector Pin Dram Pin Rank Function Block Diagram SCL SDA Event SA0 SA1 SA2D14 AC & DC Operating Conditions Dram Component Operating Temperature RangeAbsolute Maximum Ratings Absolute Maximum DC Ratings11.1 AC & DC Logic Input Levels for Single-ended Signals AC & DC Input Measurement LevelsVIH.DQDC90 Vref Tolerances Illustration of Vrefdc tolerance and Vref ac-noise limitsAC and DC Logic Input Levels for Differential Signals Differential Signals Definition35V TBD Single-ended Requirements for Differential Signals TimeDifferential Input Cross Point Voltage CK, DQS VselAC & DC Output Measurement Levels Slew Rate Definition for Single Ended Input SignalsSlew rate definition for Differential Input Signals Single Ended AC and DC Output LevelsSingle-ended Output Slew Rate SRQseDifferential Output Slew Rate Differential output slew rate definitionIDD specification definition Symbol DescriptionDatasheet M391B5773DH0 2GB256Mx72 Module DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 UnitIDD Spec Table M391B5273DH0 4GB512Mx72 ModuleInput/Output Capacitance CZQElectrical Characteristics and AC timing Refresh Parameters by Device DensityDDR3-1066 Speed Bins Speed Bin Table Notes DDR3-1600 Speed Bins CL-nRCD-nRPDatasheet Timing Parameters by Speed Grade Timing Parameters by Speed BinMIN MAX Reset Timing Jitter Notes Timing Parameter Notes ZQCorrection TSens x Tdriftrate + VSens x VdriftratePhysical Dimensions 18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH018.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0
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