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Unbuffered DIMM
datasheet
Rev. 1.0
DDR3L SDRAM
NOTE :
1)Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2)Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
3)Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4)Auto
5)
6)Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
7)IDD current measure method and detail patterns are described on DDR3 component datasheet
8)VDD and VDDQ are merged on module PCB.
9)DIMM IDD SPEC is measured with Qoff condition (IDDQ values are not considered)
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