Samsung M391B5773DH0, M391B5273DH0 specifications Datasheet

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Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

NOTE :

1)Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

2)Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

3)Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

4)Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

5)Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

6)Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device

7)IDD current measure method and detail patterns are described on DDR3 component datasheet

8)VDD and VDDQ are merged on module PCB.

9)DIMM IDD SPEC is measured with Qoff condition (IDDQ values are not considered)

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Contents Datasheet History Draft Date RevTable Of Contents Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit Key FeaturesAddress Configuration DDR3L Unbuffered Dimm Ordering InformationPin Front Back X72 Dimm Pin Configurations Front side/Back sidePin Name Description Pin DescriptionSPD and Thermal Sensor for ECC UDIMMs Input/Output Functional Description Symbol Type FunctionConnector Pin Dram Pin Rank Address Mirroring FeatureDram Pin Wiring Mirroring SCL SDA Event SA0 SA1 SA2 Function Block DiagramD14 Absolute Maximum DC Ratings Dram Component Operating Temperature RangeAbsolute Maximum Ratings AC & DC Operating ConditionsAC & DC Input Measurement Levels 11.1 AC & DC Logic Input Levels for Single-ended SignalsVIH.DQDC90 Illustration of Vrefdc tolerance and Vref ac-noise limits Vref Tolerances35V AC and DC Logic Input Levels for Differential SignalsDifferential Signals Definition TBD Time Single-ended Requirements for Differential SignalsCK, DQS Vsel Differential Input Cross Point VoltageSingle Ended AC and DC Output Levels Slew Rate Definition for Single Ended Input SignalsSlew rate definition for Differential Input Signals AC & DC Output Measurement LevelsSRQse Single-ended Output Slew RateDifferential output slew rate definition Differential Output Slew RateSymbol Description IDD specification definitionDatasheet M391B5273DH0 4GB512Mx72 Module DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 UnitIDD Spec Table M391B5773DH0 2GB256Mx72 ModuleCZQ Input/Output CapacitanceRefresh Parameters by Device Density Electrical Characteristics and AC timingDDR3-1066 Speed Bins DDR3-1600 Speed Bins CL-nRCD-nRP Speed Bin Table NotesDatasheet Timing Parameters by Speed Bin Timing Parameters by Speed GradeMIN MAX Reset Timing Jitter Notes ZQCorrection TSens x Tdriftrate + VSens x Vdriftrate Timing Parameter Notes18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH0 Physical Dimensions18.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0