Samsung M391B5273DH0, M391B5773DH0 Address Mirroring Feature, Dram Pin Wiring Mirroring

Page 8

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

7.1 Address Mirroring Feature

There is a via grid located under the DRAMs for wiring the CA signals (address, bank address, command, and control lines) to the DRAM pins. The length of the traces from the vias to the DRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces.

The pins on the DRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5, A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 DRAM pins are wired straight, with no mismatch between the connector pin assignment and the DRAM pin assignment. Some of the Rank 1 DRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight.

7.1.1 DRAM Pin Wiring Mirroring

Connector Pin

 

DRAM Pin

Rank 0

 

Rank 1

 

 

A3

A3

 

A4

 

 

 

 

A4

A4

 

A3

 

 

 

 

A5

A5

 

A6

 

 

 

 

A6

A6

 

A5

 

 

 

 

A7

A7

 

A8

 

 

 

 

A8

A8

 

A7

 

 

 

 

BA0

BA0

 

BA1

 

 

 

 

BA1

BA1

 

BA0

 

 

 

 

Figure 1illustrates the wiring in both the mirrored and non-mirrored case. The lengths of the traces to the DRAM pins, is obviously shorter. The via grid is smaller as well.

Figure 1. Wiring Differences for Mirrored and Non-Mirrored Addresses

Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limi- tations however. When writing to the internal registers with a "load mode" operation, the specific address is required. See the DDR3 UDIMM SPD specifi- cation for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank. SAMSUNG DDR3 dual rank UDIMM R/C B(2Rx8) and R/C E(2Rx8) Modules are using Mirrored Addresses mode.

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Contents Datasheet Rev History Draft DateTable Of Contents Key Features Address ConfigurationDDR3L Unbuffered Dimm Ordering Information Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UnitX72 Dimm Pin Configurations Front side/Back side Pin Front BackPin Name Description Pin DescriptionSPD and Thermal Sensor for ECC UDIMMs Symbol Type Function Input/Output Functional DescriptionConnector Pin Dram Pin Rank Address Mirroring FeatureDram Pin Wiring Mirroring Function Block Diagram SCL SDA Event SA0 SA1 SA2D14 Dram Component Operating Temperature Range Absolute Maximum RatingsAC & DC Operating Conditions Absolute Maximum DC Ratings11.1 AC & DC Logic Input Levels for Single-ended Signals AC & DC Input Measurement LevelsVIH.DQDC90 Vref Tolerances Illustration of Vrefdc tolerance and Vref ac-noise limits35V AC and DC Logic Input Levels for Differential SignalsDifferential Signals Definition TBD Single-ended Requirements for Differential Signals TimeDifferential Input Cross Point Voltage CK, DQS VselSlew Rate Definition for Single Ended Input Signals Slew rate definition for Differential Input SignalsAC & DC Output Measurement Levels Single Ended AC and DC Output LevelsSingle-ended Output Slew Rate SRQseDifferential Output Slew Rate Differential output slew rate definitionIDD specification definition Symbol DescriptionDatasheet DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 Unit IDD Spec TableM391B5773DH0 2GB256Mx72 Module M391B5273DH0 4GB512Mx72 ModuleInput/Output Capacitance CZQElectrical Characteristics and AC timing Refresh Parameters by Device DensityDDR3-1066 Speed Bins Speed Bin Table Notes DDR3-1600 Speed Bins CL-nRCD-nRPDatasheet Timing Parameters by Speed Grade Timing Parameters by Speed BinMIN MAX Reset Timing Jitter Notes Timing Parameter Notes ZQCorrection TSens x Tdriftrate + VSens x VdriftratePhysical Dimensions 18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH018.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0
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