Samsung M391B5273DH0, M391B5773DH0 specifications Tbd

Page 16

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

[ Table 4 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.35V)

	Slew Rate [V/ns]	tDVAC [ps] @ VIH/Ldiff(AC) = 320mV		tDVAC [ps] @ VIH/Ldiff(AC) = 270mV
	Slew Rate [V/ns]	min	max	min	max
		min	max	min	max
	> 4.0	TBD	-	TBD	-

	4.0	TBD	-	TBD	-

	3.0	TBD	-	TBD	-

	2.0	TBD	-	TBD	-

	1.8	TBD	-	TBD	-

	1.6	TBD	-	TBD	-

	1.4	TBD	-	TBD	-

	1.2	TBD	-	TBD	-

	1.0	TBD	-	TBD	-

	< 1.0	TBD	-	TBD	-

[ Table 5 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.5V)

	Slew Rate [V/ns]	tDVAC [ps] @ VIH/Ldiff(AC) = 350mV		tDVAC [ps] @ VIH/Ldiff(AC) = 300mV
	Slew Rate [V/ns]	min	max	min	max
		min	max	min	max
	> 4.0	75	-	175	-

	4.0	57	-	170	-

	3.0	50	-	167	-

	2.0	38	-	163	-

	1.8	34	-	162	-

	1.6	29	-	161	-

	1.4	22	-	159	-

	1.2	13	-	155	-

	1.0	0	-	150	-

	< 1.0	0	-	150	-

- 16 -

Image 16

Contents Datasheet Rev History Draft DateTable Of Contents Key Features Address ConfigurationDDR3L Unbuffered Dimm Ordering Information Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UnitX72 Dimm Pin Configurations Front side/Back side Pin Front BackSPD and Thermal Sensor for ECC UDIMMs Pin DescriptionPin Name Description Symbol Type Function Input/Output Functional DescriptionDram Pin Wiring Mirroring Address Mirroring FeatureConnector Pin Dram Pin Rank Function Block Diagram SCL SDA Event SA0 SA1 SA2D14 Dram Component Operating Temperature Range Absolute Maximum RatingsAC & DC Operating Conditions Absolute Maximum DC Ratings11.1 AC & DC Logic Input Levels for Single-ended Signals AC & DC Input Measurement LevelsVIH.DQDC90 Vref Tolerances Illustration of Vrefdc tolerance and Vref ac-noise limitsDifferential Signals Definition AC and DC Logic Input Levels for Differential Signals35V TBD Single-ended Requirements for Differential Signals TimeDifferential Input Cross Point Voltage CK, DQS VselSlew Rate Definition for Single Ended Input Signals Slew rate definition for Differential Input SignalsAC & DC Output Measurement Levels Single Ended AC and DC Output LevelsSingle-ended Output Slew Rate SRQseDifferential Output Slew Rate Differential output slew rate definitionIDD specification definition Symbol DescriptionDatasheet DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 Unit IDD Spec TableM391B5773DH0 2GB256Mx72 Module M391B5273DH0 4GB512Mx72 ModuleInput/Output Capacitance CZQElectrical Characteristics and AC timing Refresh Parameters by Device DensityDDR3-1066 Speed Bins Speed Bin Table Notes DDR3-1600 Speed Bins CL-nRCD-nRPDatasheet Timing Parameters by Speed Grade Timing Parameters by Speed BinMIN MAX Reset Timing Jitter Notes Timing Parameter Notes ZQCorrection TSens x Tdriftrate + VSens x VdriftratePhysical Dimensions 18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH018.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0