Samsung M391B5273DH0, M391B5773DH0 specifications IDD specification definition, Symbol Description

Page 22

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

13. IDD specification definition

Symbol

 

 

Description

 

Operating One Bank Active-Precharge Current

IDD0

CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: High between ACT and PRE;

Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:

 

0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

 

tern

 

Operating One Bank Active-Read-Precharge Current

IDD1

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: High between ACT, RD

and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:

 

0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

 

tern

 

 

 

Precharge Standby Current

IDD2N

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode

 

 

Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

 

Precharge Power-Down Current Slow Exit

IDD2P0

CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2);

 

 

ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit3)

 

Precharge Power-Down Current Fast Exit

IDD2P1

CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2);

 

 

ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit3)

 

Precharge Quiet Standby Current

IDD2Q

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2);

 

 

ODT Signal: stable at 0

 

 

 

Active Standby Current

IDD3N

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode

 

 

Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

 

Active Power-Down Current

IDD3P

CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT

 

 

Signal: stable at 0

 

 

 

Operating Burst Read Current

IDD4R

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: High between RD; Command, Address,

Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank

 

Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable

 

at 0; Pattern Details: Refer to Component Datasheet for detail pattern

 

Operating Burst Write Current

IDD4W

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: High between WR; Command, Address,

Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank

 

Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable

 

at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern

 

Burst Refresh Current

IDD5B

CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: High between REF; Command,

Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and

 

 

RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

 

Self Refresh Current: Normal Temperature Range

IDD6

TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and

CK:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

 

 

Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING

 

Self-Refresh Current: Extended Temperature Range (optional)6)

IDD6ET

TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and

CK:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

 

 

Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING

 

Operating Bank Interleave Read Current

 

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: CL-1;

CS

: High

IDD7

between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and

 

the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:

 

Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

 

RESET Low Current

IDD8

RESET : Low; External clock : off; CK and

CK

: LOW; CKE : FLOATING ;

CS,

Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :

 

FLOATING

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Contents Datasheet Rev History Draft DateTable Of Contents DDR3L Unbuffered Dimm Ordering Information Key FeaturesAddress Configuration Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UnitX72 Dimm Pin Configurations Front side/Back side Pin Front BackSPD and Thermal Sensor for ECC UDIMMs Pin DescriptionPin Name Description Symbol Type Function Input/Output Functional DescriptionDram Pin Wiring Mirroring Address Mirroring FeatureConnector Pin Dram Pin Rank Function Block Diagram SCL SDA Event SA0 SA1 SA2D14 AC & DC Operating Conditions Dram Component Operating Temperature RangeAbsolute Maximum Ratings Absolute Maximum DC Ratings11.1 AC & DC Logic Input Levels for Single-ended Signals AC & DC Input Measurement LevelsVIH.DQDC90 Vref Tolerances Illustration of Vrefdc tolerance and Vref ac-noise limitsDifferential Signals Definition AC and DC Logic Input Levels for Differential Signals35V TBD Single-ended Requirements for Differential Signals TimeDifferential Input Cross Point Voltage CK, DQS VselAC & DC Output Measurement Levels Slew Rate Definition for Single Ended Input SignalsSlew rate definition for Differential Input Signals Single Ended AC and DC Output LevelsSingle-ended Output Slew Rate SRQseDifferential Output Slew Rate Differential output slew rate definitionIDD specification definition Symbol DescriptionDatasheet M391B5773DH0 2GB256Mx72 Module DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 UnitIDD Spec Table M391B5273DH0 4GB512Mx72 ModuleInput/Output Capacitance CZQElectrical Characteristics and AC timing Refresh Parameters by Device DensityDDR3-1066 Speed Bins Speed Bin Table Notes DDR3-1600 Speed Bins CL-nRCD-nRPDatasheet Timing Parameters by Speed Grade Timing Parameters by Speed BinMIN MAX Reset Timing Jitter Notes Timing Parameter Notes ZQCorrection TSens x Tdriftrate + VSens x VdriftratePhysical Dimensions 18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH018.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0
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