datasheet
Rev. 1.0
DDR3L SDRAM
11.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every half-cycle.
DQS, DQS have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle proceeding and follow- ing a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD
signals, then these ac-levels apply also for the single-ended signals CK and CK .
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
VSEL max
VSS or VSSQ
CK or DQS
VSEL
time
Figure 4. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single- ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.
[ Table 6 ] Single ended levels for CK, DQS, CK, DQS
Symbol | Parameter | | DDR3-800/1066/1333/1600 | Unit | NOTE |
| Min | Max |
| | | | | | | |
VSEH | Single-ended high-level for strobes | | (VDD/2)+0.175 | NOTE 3 | V | 1, 2 |
| | | | | (VDD/2)+0.175 | | | |
Single-ended high-level for CK, CK | | NOTE 3 | V | 1, 2 |
| |
VSEL | Single-ended low-level for strobes | | NOTE 3 | (VDD/2)-0.175 | V | 1, 2 |
| | | | | | (VDD/2)-0.175 | | |
Single-ended low-level for CK, CK | | NOTE 3 | V | 1, 2 |
| |
NOTE :
1.For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.
2.VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here
3.These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig- nals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"
- 17 -
