Samsung M391B5773DH0 X72 Dimm Pin Configurations Front side/Back side, Pin Front Back

Page 5

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

4. x72 DIMM Pin Configurations (Front side/Back side)

Pin	Front				Pin	Back	Pin			Front							Pin		Back											Pin	Front			Pin	Back
1	VREFDQ				121	VSS	42					NC					162				NC									82		DQ33		202	VSS
2		VSS			122	DQ4	43					NC					163				VSS									83		VSS		203	DM4
3		DQ0			123	DQ5	44				VSS						164				CB6									84				204	NC
																																DQS4
4		DQ1			124	VSS	45				CB2						165				CB7									85	DQS4			205	VSS
5		VSS			125	DM0	46				CB3						166				VSS									86		VSS		206	DQ38
6					126	NC	47				VSS						167	NC (TEST)3												87		DQ34		207	DQ39
		DQS0
7		DQS0			127	VSS	48					NC					168													88		DQ35		208	VSS
																				Reset
8		VSS			128	DQ6										KEY														89		VSS		209	DQ44
9		DQ2			129	DQ7	49					NC					169	CKE1,NC1												90		DQ40		210	DQ45
10		DQ3			130	VSS	50			CKE0							170				VDD									91		DQ41		211	VSS
11		VSS			131	DQ12	51				VDD						171				NC									92		VSS		212	DM5
12		DQ8			132	DQ13	52				BA2						172				A14									93				213	NC
																																DQS5
13		DQ9			133	VSS	53					NC					173				VDD									94		DQS5		214	VSS
14		VSS			134	DM1	54				VDD						174													95		VSS		215	DQ46
																		A12/BC
15					135	NC	55				A11						175					A9								96		DQ42		216	DQ47
		DQS1
16		DQS1			136	VSS	56						A7				176				VDD									97		DQ43		217	VSS
17		VSS			137	DQ14	57				VDD						177					A8								98		VSS		218	DQ52
18		DQ10			138	DQ15	58						A5				178				A6									99		DQ48		219	DQ53

19		DQ11			139	VSS	59						A4				179				VDD									100		DQ49		220	VSS
20		VSS			140	DQ20	60				VDD						180					A3								101		VSS		221	DM6
21		DQ16			141	DQ21	61						A2				181				A1									102				222	NC
																																DQS6

22		DQ17			142	VSS	62				VDD						182				VDD									103		DQS6		223	VSS
23		VSS			143	DM2	63		CK1,NC2								183				VDD									104		VSS		224	DQ54
24					144	NC	64										184				CK0									105		DQ50		225	DQ55
		DQS2
									CK1,NC2
25		DQS2			145	VSS	65				VDD						185													106		DQ51		226	VSS
																					CK0
26		VSS			146	DQ22	66				VDD						186				VDD									107		VSS		227	DQ60
27		DQ18			147	DQ23	67			VREFCA							187													108		DQ56		228	DQ61
																			EVENT
28		DQ19			148	VSS	68					NC					188				A0									109		DQ57		229	VSS
29		VSS			149	DQ28	69				VDD						189				VDD									110		VSS		230	DM7
30		DQ24			150	DQ29	70			A10/AP							190				BA1									111				231	NC
																																DQS7

31		DQ25			151	VSS	71				BA0						191				VDD									112		DQS7		232	VSS
32		VSS			152	DM3	72				VDD						192													113		VSS		233	DQ62
																					RAS
33					153	NC	73										193													114		DQ58		234	DQ63
		DQS3										WE										S0

34		DQS3			154	VSS	74										194				VDD									115		DQ59		235	VSS
											CAS
35		VSS			155	DQ30	75				VDD						195		ODT0											116		VSS		236	VDDSPD
36		DQ26			156	DQ31	76										196				A13									117		SA0		237	SA1
										S1, NC1
37		DQ27			157	VSS	77	ODT1, NC1									197				VDD									118		SCL		238	SDA
38		VSS			158	CB4	78				VDD						198				NC									119		SA2		239	VSS
39		CB0			159	CB5	79					NC					199				VSS									120		VTT		240	VTT
40		CB1			160	VSS	80				VSS						200			DQ36
41		VSS			161	DM8	81			DQ32							201		DQ37

NOTE :

NC = No Connect; NU = Not Used; RFU = Reserved Future Use

1.S1, ODT1, CKE1: Used for dual-rank UDIMMs; NC on single-rank UDIMMs

2.CK1,NC and CK1,NC : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated

3.TEST (pin 167) used by memory bus analysis tools (unused on memory DIMMs)

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

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Image 5

Contents

Datasheet History Draft Date RevTable Of Contents Address Configuration Key FeaturesDDR3L Unbuffered Dimm Ordering Information Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UnitPin Front Back X72 Dimm Pin Configurations Front side/Back sidePin Name Description Pin DescriptionSPD and Thermal Sensor for ECC UDIMMs Input/Output Functional Description Symbol Type FunctionConnector Pin Dram Pin Rank Address Mirroring FeatureDram Pin Wiring Mirroring SCL SDA Event SA0 SA1 SA2 Function Block DiagramD14 Absolute Maximum Ratings Dram Component Operating Temperature RangeAC & DC Operating Conditions Absolute Maximum DC RatingsAC & DC Input Measurement Levels 11.1 AC & DC Logic Input Levels for Single-ended SignalsVIH.DQDC90 Illustration of Vrefdc tolerance and Vref ac-noise limits Vref Tolerances35V AC and DC Logic Input Levels for Differential SignalsDifferential Signals Definition TBD Time Single-ended Requirements for Differential SignalsCK, DQS Vsel Differential Input Cross Point VoltageSlew rate definition for Differential Input Signals Slew Rate Definition for Single Ended Input SignalsAC & DC Output Measurement Levels Single Ended AC and DC Output LevelsSRQse Single-ended Output Slew RateDifferential output slew rate definition Differential Output Slew RateSymbol Description IDD specification definitionDatasheet IDD Spec Table DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 UnitM391B5773DH0 2GB256Mx72 Module M391B5273DH0 4GB512Mx72 ModuleCZQ Input/Output CapacitanceRefresh Parameters by Device Density Electrical Characteristics and AC timingDDR3-1066 Speed Bins DDR3-1600 Speed Bins CL-nRCD-nRP Speed Bin Table NotesDatasheet Timing Parameters by Speed Bin Timing Parameters by Speed GradeMIN MAX Reset Timing Jitter Notes ZQCorrection TSens x Tdriftrate + VSens x Vdriftrate Timing Parameter Notes18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH0 Physical Dimensions18.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0

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