Samsung M391B5273DH0, M391B5773DH0 specifications AC & DC Input Measurement Levels

Page 12

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

11. AC & DC Input Measurement Levels

11.1 AC & DC Logic Input Levels for Single-ended Signals

[ Table 2 ] Single Ended AC and DC input levels for Command and Address

Symbol

Parameter

DDR3-800/1066/1333/1600

 

Unit

NOTE

Min.

 

Max.

 

 

 

 

 

 

 

1.35V

 

 

 

VIH.CA(DC90)

DC input logic high

VREF + 90

 

VDD

mV

1,5a)

VIL.CA(DC90)

DC input logic low

VSS

 

VREF - 90

mV

1,6a)

VIH.CA(AC160)

AC input logic high

VREF + 160

 

Note 2

mV

1,2

VIL.CA(AC160)

AC input logic low

Note 2

 

VREF - 160

mV

1,2

VIH.CA(AC135)

AC input logic high

VREF+135

 

Note 2

mV

1,2

VIL.CA(AC135)

AC input logic lowM

Note 2

 

VREF-135

mV

1,2

VREFCA(DC)

Reference Voltage for ADD,

0.49*VDD

 

0.51*VDD

V

3,4

CMD inputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.5V

 

 

 

VIH.CA(DC100)

DC input logic high

VREF + 100

 

VDD

mV

1,5b)

VIL.CA(DC100)

DC input logic low

VSS

 

VREF - 100

mV

1,6b)

VIH.CA(AC175)

AC input logic high

VREF + 175

 

Note 2

mV

1,2,7

VIL.CA(AC175)

AC input logic low

Note 2

 

VREF - 175

mV

1,2,8

VIH.CA(AC150)

AC input logic high

VREF+150

 

Note 2

mV

1,2,7

VIL.CA(AC150)

AC input logic low

Note 2

 

VREF-150

mV

1,2,8

VREFCA(DC)

Reference Voltage for ADD,

0.49*VDD

 

0.51*VDD

V

3,4

CMD inputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE :

1.For input only pins except RESET, VREF = VREFCA(DC)

2.See "Overshoot and Undershoot specifications" section.

3.The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)

4.For reference : approx. VDD/2 ± 15mV

5.VIH(dc) is used as a simplified symbol for VIH.CA(a) 1.35V : DC90, b) 1.5V : DC100)

6.VIL(dc) is used as a simplified symbol for VIL.CA(a) 1.35V : DC90, b) 1.5V : DC100)

7.VIH(ac) is used as a simplified symbol for VIH.CA(AC175) and VIH.CA(AC150); VIH.CA(AC175) value is used when VREF + 175mV is referenced and VIH.CA(AC150) value is used when VREF + 150mV is referenced.

8.VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150); VIL.CA(AC175) value is used when VREF - 175mV is referenced and VIL.CA(AC150) value is used when VREF - 150mV is referenced.

- 12 -

Image 12
Contents Datasheet Rev History Draft DateTable Of Contents Key Features Address ConfigurationDDR3L Unbuffered Dimm Ordering Information Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UnitX72 Dimm Pin Configurations Front side/Back side Pin Front BackPin Description SPD and Thermal Sensor for ECC UDIMMsPin Name Description Symbol Type Function Input/Output Functional DescriptionAddress Mirroring Feature Dram Pin Wiring MirroringConnector Pin Dram Pin Rank Function Block Diagram SCL SDA Event SA0 SA1 SA2D14 Dram Component Operating Temperature Range Absolute Maximum RatingsAC & DC Operating Conditions Absolute Maximum DC Ratings11.1 AC & DC Logic Input Levels for Single-ended Signals AC & DC Input Measurement LevelsVIH.DQDC90 Vref Tolerances Illustration of Vrefdc tolerance and Vref ac-noise limitsAC and DC Logic Input Levels for Differential Signals Differential Signals Definition35V TBD Single-ended Requirements for Differential Signals TimeDifferential Input Cross Point Voltage CK, DQS VselSlew Rate Definition for Single Ended Input Signals Slew rate definition for Differential Input SignalsAC & DC Output Measurement Levels Single Ended AC and DC Output LevelsSingle-ended Output Slew Rate SRQseDifferential Output Slew Rate Differential output slew rate definitionIDD specification definition Symbol DescriptionDatasheet DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 Unit IDD Spec TableM391B5773DH0 2GB256Mx72 Module M391B5273DH0 4GB512Mx72 ModuleInput/Output Capacitance CZQElectrical Characteristics and AC timing Refresh Parameters by Device DensityDDR3-1066 Speed Bins Speed Bin Table Notes DDR3-1600 Speed Bins CL-nRCD-nRPDatasheet Timing Parameters by Speed Grade Timing Parameters by Speed BinMIN MAX Reset Timing Jitter Notes Timing Parameter Notes ZQCorrection TSens x Tdriftrate + VSens x VdriftratePhysical Dimensions 18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH018.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0