Samsung M391B5773DH0, M391B5273DH0 AC and DC Logic Input Levels for Differential Signals, 35V

Page 15

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

11.3 AC and DC Logic Input Levels for Differential Signals

11.3.1 Differential Signals Definition

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDVAC

 

CK-CK)

 

VIH.DIFF.AC.MIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIH.DIFF.MIN

 

DQS-DQS,

 

 

 

0.0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(i.e.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

half cycle

Voltage

 

VIL.DIFF.MAX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Differential

 

VIL.DIFF.AC.MAX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDVAC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3. Definition of differential ac-swing and "time above ac level" tDVAC

11.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

 

 

 

DDR3-800/1066/1333/1600

 

 

 

Symbol

Parameter

1.35V

1.5V

unit

NOTE

 

 

min

max

min

max

 

 

VIHdiff

differential input high

+0.18

NOTE 3

+0.20

NOTE 3

V

1

VILdiff

differential input low

NOTE 3

-0.18

NOTE 3

-0.20

V

1

VIHdiff(AC)

differential input high ac

2 x (VIH(AC) - VREF)

NOTE 3

2 x (VIH(AC) - VREF)

NOTE 3

V

2

VILdiff(AC)

differential input low ac

NOTE 3

2 x (VIL(AC) - VREF)

NOTE 3

2 x (VIL(AC) - VREF)

V

2

NOTE :

1.Used to define a differential signal slew-rate.

2.for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.

3.These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig-

nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"

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Contents
Datasheet History Draft Date RevTable Of Contents Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit Key FeaturesAddress Configuration DDR3L Unbuffered Dimm Ordering InformationPin Front Back X72 Dimm Pin Configurations Front side/Back sidePin Description SPD and Thermal Sensor for ECC UDIMMsPin Name Description Input/Output Functional Description Symbol Type FunctionAddress Mirroring Feature Dram Pin Wiring MirroringConnector Pin Dram Pin Rank SCL SDA Event SA0 SA1 SA2 Function Block DiagramD14 Absolute Maximum DC Ratings Dram Component Operating Temperature RangeAbsolute Maximum Ratings AC & DC Operating ConditionsAC & DC Input Measurement Levels 11.1 AC & DC Logic Input Levels for Single-ended SignalsVIH.DQDC90 Illustration of Vrefdc tolerance and Vref ac-noise limits Vref TolerancesAC and DC Logic Input Levels for Differential Signals Differential Signals Definition35V TBD Time Single-ended Requirements for Differential SignalsCK, DQS Vsel Differential Input Cross Point VoltageSingle Ended AC and DC Output Levels Slew Rate Definition for Single Ended Input SignalsSlew rate definition for Differential Input Signals AC & DC Output Measurement LevelsSRQse Single-ended Output Slew RateDifferential output slew rate definition Differential Output Slew RateSymbol Description IDD specification definitionDatasheet M391B5273DH0 4GB512Mx72 Module DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 UnitIDD Spec Table M391B5773DH0 2GB256Mx72 ModuleCZQ Input/Output CapacitanceRefresh Parameters by Device Density Electrical Characteristics and AC timingDDR3-1066 Speed Bins DDR3-1600 Speed Bins CL-nRCD-nRP Speed Bin Table NotesDatasheet Timing Parameters by Speed Bin Timing Parameters by Speed GradeMIN MAX Reset Timing Jitter Notes ZQCorrection TSens x Tdriftrate + VSens x Vdriftrate Timing Parameter Notes18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH0 Physical Dimensions18.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0
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