Samsung M391B5773DH0 AC & DC Output Measurement Levels, Single Ended AC and DC Output Levels

Page 19

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

11.4 Slew Rate Definition for Single Ended Input Signals

See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals. See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.

11.5 Slew rate definition for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.

[ Table 9 ] Differential input slew rate definition

Description

Measured

 

Defined by

From

 

To

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VILdiffmax

 

VIHdiffmin

 

VIHdiffmin - VILdiffmax

 

Differential input slew rate for rising edge (CK-CK and DQS-DQS)

 

 

 

Delta TRdiff

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIHdiffmin

 

VILdiffmax

 

VIHdiffmin - VILdiffmax

 

Differential input slew rate for falling edge (CK-CK and DQS-DQS)

 

 

 

Delta TFdiff

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE : The differential signal (i.e. CK -

 

and DQS -

 

 

 

must be linear between these thresholds

 

 

 

 

CK

DQS)

 

 

 

 

 

VIHdiffmin

 

0

 

VILdiffmax

delta TFdiff

delta TRdiff

Figure 6. Differential input slew rate definition for DQS, DQS and CK, CK

12. AC & DC Output Measurement Levels

12.1 Single Ended AC and DC Output Levels

[ Table 10 ] Single Ended AC and DC output levels

Symbol

Parameter

DDR3-800/1066/1333/1600

Units

NOTE

VOH(DC)

DC output high measurement level (for IV curve linearity)

0.8 x VDDQ

V

 

VOM(DC)

DC output mid measurement level (for IV curve linearity)

0.5 x VDDQ

V

 

VOL(DC)

DC output low measurement level (for IV curve linearity)

0.2 x VDDQ

V

 

VOH(AC)

AC output high measurement level (for output SR)

VTT + 0.1 x VDDQ

V

1

VOL(AC)

AC output low measurement level (for output SR)

VTT - 0.1 x VDDQ

V

1

NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2.

12.2 Differential AC and DC Output Levels

[ Table 11 ] Differential AC and DC output levels

Symbol

Parameter

DDR3-800/1066/1333/1600

Units

NOTE

VOHdiff(AC)

AC differential output high measurement level (for output SR)

+0.2 x VDDQ

V

1

VOLdiff(AC)

AC differential output low measurement level (for output SR)

-0.2 x VDDQ

V

1

NOTE : 1. The swing of +/-0.2xVDDQis based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs.

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Contents
Datasheet History Draft Date RevTable Of Contents Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit Key FeaturesAddress Configuration DDR3L Unbuffered Dimm Ordering InformationPin Front Back X72 Dimm Pin Configurations Front side/Back sideSPD and Thermal Sensor for ECC UDIMMs Pin DescriptionPin Name Description Input/Output Functional Description Symbol Type FunctionDram Pin Wiring Mirroring Address Mirroring FeatureConnector Pin Dram Pin Rank SCL SDA Event SA0 SA1 SA2 Function Block DiagramD14 Absolute Maximum DC Ratings Dram Component Operating Temperature RangeAbsolute Maximum Ratings AC & DC Operating ConditionsAC & DC Input Measurement Levels 11.1 AC & DC Logic Input Levels for Single-ended SignalsVIH.DQDC90 Illustration of Vrefdc tolerance and Vref ac-noise limits Vref TolerancesDifferential Signals Definition AC and DC Logic Input Levels for Differential Signals35V TBD Time Single-ended Requirements for Differential SignalsCK, DQS Vsel Differential Input Cross Point VoltageSingle Ended AC and DC Output Levels Slew Rate Definition for Single Ended Input SignalsSlew rate definition for Differential Input Signals AC & DC Output Measurement LevelsSRQse Single-ended Output Slew RateDifferential output slew rate definition Differential Output Slew RateSymbol Description IDD specification definitionDatasheet M391B5273DH0 4GB512Mx72 Module DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 UnitIDD Spec Table M391B5773DH0 2GB256Mx72 ModuleCZQ Input/Output CapacitanceRefresh Parameters by Device Density Electrical Characteristics and AC timingDDR3-1066 Speed Bins DDR3-1600 Speed Bins CL-nRCD-nRP Speed Bin Table NotesDatasheet Timing Parameters by Speed Bin Timing Parameters by Speed GradeMIN MAX Reset Timing Jitter Notes ZQCorrection TSens x Tdriftrate + VSens x Vdriftrate Timing Parameter Notes18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH0 Physical Dimensions18.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0
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