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Unbuffered DIMM
datasheet
Rev. 1.0
DDR3L SDRAM
[ Table 20 ] DDR3-1600 Speed Bins
Speed |
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Parameter |
| Symbol | min |
| max |
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Intermal read command to first data |
| tAA | 13.75 |
| 20 | ns |
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| (13.125)8 |
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ACT to internal read or write delay time | tRCD | 13.75 |
| - | ns |
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(13.125)8 |
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PRE command period |
| tRP | 13.75 |
| - | ns |
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| (13.125)8 |
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ACT to ACT or REF command period | tRC | 48.75 |
| - | ns |
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(48.125)8 |
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ACT to PRE command period |
| tRAS | 35 |
| 9*tREFI | ns |
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| CWL = 5 | tCK(AVG) | 2.5 |
| 3.3 | ns | 1,2,3,7 |
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CL = 6 |
| CWL = 6 | tCK(AVG) |
| Reserved | ns | 1,2,3,4,7 | |
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| CWL = 7, 8 | tCK(AVG) |
| Reserved | ns | 4 | |
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| CWL = 5 | tCK(AVG) |
| Reserved | ns | 4 | |
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CL = 7 |
| CWL = 6 | tCK(AVG) | 1.875 |
| <2.5 | ns | 1,2,3,4,7 |
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| CWL = 7 | tCK(AVG) |
| Reserved | ns | 1,2,3,4,7 | ||
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| CWL = 8 | tCK(AVG) |
| Reserved | ns | 4 | |
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| CWL = 5 | tCK(AVG) |
| Reserved | ns | 4 | |
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CL = 8 |
| CWL = 6 | tCK(AVG) | 1.875 |
| <2.5 | ns | 1,2,3,7 |
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| CWL = 7 | tCK(AVG) |
| Reserved | ns | 1,2,3,4,7 | ||
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| CWL = 8 | tCK(AVG) |
| Reserved | ns | 1,2,3,4 | |
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| CWL = 5,6 | tCK(AVG) |
| Reserved | ns | 4 | |
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CL = 9 |
| CWL = 7 | tCK(AVG) | 1.5 |
| <1.875 | ns | 1,2,3,4,7 |
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| CWL = 8 | tCK(AVG) |
| Reserved | ns | 1,2,3,4 | |
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| CWL = 5,6 | tCK(AVG) |
| Reserved | ns | 4 | |
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CL = 10 |
| CWL = 7 | tCK(AVG) | 1.5 |
| <1.875 | ns | 1,2,3,7 |
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| CWL = 8 | tCK(AVG) |
| Reserved | ns | 1,2,3,4 | |
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CL = 11 |
| CWL = 5,6,7 | tCK(AVG) |
| Reserved | ns | 4 | |
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| CWL = 8 | tCK(AVG) | 1.25 |
| <1.5 | ns | 1,2,3,8 | |
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Supported CL Settings |
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| 6,7,8,9,10,11 | nCK |
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Supported CWL Settings |
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| 5,6,7,8 | nCK |
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16.3.1 Speed Bin Table Notes
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