Samsung M391B5273DH0, M391B5773DH0 Speed Bin Table Notes, DDR3-1600 Speed Bins CL-nRCD-nRP

Page 28

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

[ Table 20 ] DDR3-1600 Speed Bins

Speed

 

 

DDR3-1600

 

 

CL-nRCD-nRP

 

 

11-11-11

Units

NOTE

Parameter

 

Symbol

min

 

max

 

 

Intermal read command to first data

 

tAA

13.75

 

20

ns

 

 

(13.125)8

 

 

 

 

 

 

 

 

 

 

ACT to internal read or write delay time

tRCD

13.75

 

-

ns

 

(13.125)8

 

 

 

 

 

 

 

 

 

 

PRE command period

 

tRP

13.75

 

-

ns

 

 

(13.125)8

 

 

 

 

 

 

 

 

 

 

ACT to ACT or REF command period

tRC

48.75

 

-

ns

 

(48.125)8

 

 

 

 

 

 

 

 

 

 

ACT to PRE command period

 

tRAS

35

 

9*tREFI

ns

 

 

 

 

 

 

 

 

 

 

 

 

CWL = 5

tCK(AVG)

2.5

 

3.3

ns

1,2,3,7

 

 

 

 

 

 

 

 

 

CL = 6

 

CWL = 6

tCK(AVG)

 

Reserved

ns

1,2,3,4,7

 

 

 

 

 

 

 

 

 

 

CWL = 7, 8

tCK(AVG)

 

Reserved

ns

4

 

 

 

 

 

 

 

 

 

 

CWL = 5

tCK(AVG)

 

Reserved

ns

4

 

 

 

 

 

 

 

 

CL = 7

 

CWL = 6

tCK(AVG)

1.875

 

<2.5

ns

1,2,3,4,7

 

 

 

 

 

 

 

 

 

CWL = 7

tCK(AVG)

 

Reserved

ns

1,2,3,4,7

 

 

 

 

 

 

 

 

 

 

 

 

 

CWL = 8

tCK(AVG)

 

Reserved

ns

4

 

 

 

 

 

 

 

 

 

 

CWL = 5

tCK(AVG)

 

Reserved

ns

4

 

 

 

 

 

 

 

 

CL = 8

 

CWL = 6

tCK(AVG)

1.875

 

<2.5

ns

1,2,3,7

 

 

 

 

 

 

 

 

 

CWL = 7

tCK(AVG)

 

Reserved

ns

1,2,3,4,7

 

 

 

 

 

 

 

 

 

 

 

 

 

CWL = 8

tCK(AVG)

 

Reserved

ns

1,2,3,4

 

 

 

 

 

 

 

 

 

 

CWL = 5,6

tCK(AVG)

 

Reserved

ns

4

 

 

 

 

 

 

 

 

CL = 9

 

CWL = 7

tCK(AVG)

1.5

 

<1.875

ns

1,2,3,4,7

 

 

 

 

 

 

 

 

 

 

 

CWL = 8

tCK(AVG)

 

Reserved

ns

1,2,3,4

 

 

 

 

 

 

 

 

 

 

CWL = 5,6

tCK(AVG)

 

Reserved

ns

4

 

 

 

 

 

 

 

 

CL = 10

 

CWL = 7

tCK(AVG)

1.5

 

<1.875

ns

1,2,3,7

 

 

 

 

 

 

 

 

 

 

 

CWL = 8

tCK(AVG)

 

Reserved

ns

1,2,3,4

 

 

 

 

 

 

 

 

CL = 11

 

CWL = 5,6,7

tCK(AVG)

 

Reserved

ns

4

 

 

 

 

 

 

 

 

 

CWL = 8

tCK(AVG)

1.25

 

<1.5

ns

1,2,3,8

 

 

 

 

 

 

 

 

 

 

 

 

Supported CL Settings

 

 

 

6,7,8,9,10,11

nCK

 

 

 

 

 

 

 

 

Supported CWL Settings

 

 

 

5,6,7,8

nCK

 

 

 

 

 

 

 

 

 

 

16.3.1 Speed Bin Table Notes

- 28 -

Page 27 Page 29
Image 28
Page 27 Page 29
Contents
Datasheet Rev History Draft DateTable Of Contents Key Features Address ConfigurationDDR3L Unbuffered Dimm Ordering Information Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UnitX72 Dimm Pin Configurations Front side/Back side Pin Front BackSPD and Thermal Sensor for ECC UDIMMs Pin DescriptionPin Name Description Symbol Type Function Input/Output Functional DescriptionDram Pin Wiring Mirroring Address Mirroring FeatureConnector Pin Dram Pin Rank Function Block Diagram SCL SDA Event SA0 SA1 SA2D14 Dram Component Operating Temperature Range Absolute Maximum RatingsAC & DC Operating Conditions Absolute Maximum DC Ratings11.1 AC & DC Logic Input Levels for Single-ended Signals AC & DC Input Measurement LevelsVIH.DQDC90 Vref Tolerances Illustration of Vrefdc tolerance and Vref ac-noise limitsDifferential Signals Definition AC and DC Logic Input Levels for Differential Signals35V TBD Single-ended Requirements for Differential Signals TimeDifferential Input Cross Point Voltage CK, DQS VselSlew Rate Definition for Single Ended Input Signals Slew rate definition for Differential Input SignalsAC & DC Output Measurement Levels Single Ended AC and DC Output LevelsSingle-ended Output Slew Rate SRQseDifferential Output Slew Rate Differential output slew rate definitionIDD specification definition Symbol DescriptionDatasheet DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 Unit IDD Spec TableM391B5773DH0 2GB256Mx72 Module M391B5273DH0 4GB512Mx72 ModuleInput/Output Capacitance CZQElectrical Characteristics and AC timing Refresh Parameters by Device DensityDDR3-1066 Speed Bins Speed Bin Table Notes DDR3-1600 Speed Bins CL-nRCD-nRPDatasheet Timing Parameters by Speed Grade Timing Parameters by Speed BinMIN MAX Reset Timing Jitter Notes Timing Parameter Notes ZQCorrection TSens x Tdriftrate + VSens x VdriftratePhysical Dimensions 18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH018.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0
Related manuals
Manual 36 pages 22.54 Kb