Samsung M391B5773DH0, M391B5273DH0 specifications DDR3-1066 Speed Bins

Page 27

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

[ Table 18 ] DDR3-1066 Speed Bins

Speed

 

 

DDR3-1066

 

 

 

CL-nRCD-nRP

 

7 - 7 - 7

 

Units

NOTE

Parameter

 

Symbol

min

 

 

max

 

 

Internal read command to first data

 

tAA

13.125

 

 

20

ns

 

 

 

 

 

 

 

 

 

 

ACT to internal read or write delay time

tRCD

13.125

 

 

-

ns

 

 

 

 

 

 

 

 

 

 

 

PRE command period

 

tRP

13.125

 

 

-

ns

 

 

 

 

 

 

 

 

 

 

ACT to ACT or REF command period

tRC

50.625

 

 

-

ns

 

 

 

 

 

 

 

 

 

 

 

ACT to PRE command period

 

tRAS

37.5

 

 

9*tREFI

ns

 

 

 

 

 

 

 

 

 

 

 

 

CL = 6

 

CWL = 5

tCK(AVG)

2.5

 

 

3.3

ns

1,2,3,5

 

 

 

 

 

 

 

 

 

 

CWL = 6

tCK(AVG)

Reserved

 

ns

1,2,3,4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CL = 7

 

CWL = 5

tCK(AVG)

Reserved

 

ns

4

 

 

 

 

 

 

 

 

 

 

CWL = 6

tCK(AVG)

1.875

 

 

<2.5

ns

1,2,3,4,8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CL = 8

 

CWL = 5

tCK(AVG)

Reserved

 

ns

4

 

 

 

 

 

 

 

 

 

 

CWL = 6

tCK(AVG)

1.875

 

 

<2.5

ns

1,2,3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Supported CL Settings

 

 

6,7,8

 

nCK

 

 

 

 

 

 

 

 

 

 

Supported CWL Settings

 

 

5,6

 

nCK

 

 

 

 

 

 

 

 

 

 

 

 

[ Table 19 ] DDR3-1333 Speed Bins

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Speed

 

 

DDR3-1333

 

 

 

CL-nRCD-nRP

 

9 -9 - 9

 

Units

NOTE

Parameter

 

Symbol

min

 

max

 

 

Internal read command to first data

 

tAA

13.5 (13.125)8

 

 

20

ns

 

ACT to internal read or write delay time

tRCD

13.5 (13.125)8

 

 

-

ns

 

PRE command period

 

tRP

13.5 (13.125)8

 

 

-

ns

 

ACT to ACT or REF command period

tRC

49.5 (49.125)8

 

 

-

ns

 

ACT to PRE command period

 

tRAS

36

 

 

9*tREFI

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CWL = 5

tCK(AVG)

2.5

 

 

3.3

ns

1,2,3,6

 

 

 

 

 

 

 

 

 

CL = 6

 

 

CWL = 6

tCK(AVG)

Reserved

 

ns

1,2,3,4,6

 

 

 

 

 

 

 

 

 

 

 

 

CWL = 7

tCK(AVG)

Reserved

 

ns

4

 

 

 

 

 

 

 

 

 

 

 

 

CWL = 5

tCK(AVG)

Reserved

 

ns

4

 

 

 

 

 

 

 

 

 

 

CL = 7

 

 

CWL = 6

tCK(AVG)

1.875

 

 

<2.5

ns

1,2,3,4,6

 

 

 

 

 

 

 

 

 

 

 

 

 

CWL = 7

tCK(AVG)

Reserved

 

ns

1,2,3,4

 

 

 

 

 

 

 

 

 

 

 

 

CWL = 5

tCK(AVG)

Reserved

 

ns

4

 

 

 

 

 

 

 

 

 

 

CL = 8

 

 

CWL = 6

tCK(AVG)

1.875

 

 

<2.5

ns

1,2,3,6

 

 

 

 

 

 

 

 

 

 

 

 

 

CWL = 7

tCK(AVG)

Reserved

 

ns

1,2,3,4

 

 

 

 

 

 

 

 

 

CL = 9

 

 

CWL = 5,6

tCK(AVG)

Reserved

 

ns

4

 

 

 

 

 

 

 

 

 

 

 

CWL = 7

tCK(AVG)

1.5

 

 

<1.875

ns

1,2,3,4,8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CL = 10

 

 

CWL = 5,6

tCK(AVG)

Reserved

 

ns

4

 

 

 

 

 

 

 

 

 

 

 

CWL = 7

tCK(AVG)

Reserved

 

ns

1,2,3

 

 

 

 

 

 

 

 

 

 

 

 

 

Supported CL Settings

 

 

6,7,8,9

 

nCK

 

 

 

 

 

 

 

 

Supported CWL Settings

 

 

5,6,7

 

nCK

 

 

 

 

 

 

 

 

 

 

 

 

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Contents Datasheet History Draft Date RevTable Of Contents Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit Key FeaturesAddress Configuration DDR3L Unbuffered Dimm Ordering InformationPin Front Back X72 Dimm Pin Configurations Front side/Back sidePin Description SPD and Thermal Sensor for ECC UDIMMsPin Name Description Input/Output Functional Description Symbol Type FunctionAddress Mirroring Feature Dram Pin Wiring MirroringConnector Pin Dram Pin Rank SCL SDA Event SA0 SA1 SA2 Function Block DiagramD14 Absolute Maximum DC Ratings Dram Component Operating Temperature RangeAbsolute Maximum Ratings AC & DC Operating ConditionsAC & DC Input Measurement Levels 11.1 AC & DC Logic Input Levels for Single-ended SignalsVIH.DQDC90 Illustration of Vrefdc tolerance and Vref ac-noise limits Vref TolerancesAC and DC Logic Input Levels for Differential Signals Differential Signals Definition35V TBD Time Single-ended Requirements for Differential SignalsCK, DQS Vsel Differential Input Cross Point VoltageSingle Ended AC and DC Output Levels Slew Rate Definition for Single Ended Input SignalsSlew rate definition for Differential Input Signals AC & DC Output Measurement LevelsSRQse Single-ended Output Slew RateDifferential output slew rate definition Differential Output Slew RateSymbol Description IDD specification definitionDatasheet M391B5273DH0 4GB512Mx72 Module DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 UnitIDD Spec Table M391B5773DH0 2GB256Mx72 ModuleCZQ Input/Output CapacitanceRefresh Parameters by Device Density Electrical Characteristics and AC timingDDR3-1066 Speed Bins DDR3-1600 Speed Bins CL-nRCD-nRP Speed Bin Table NotesDatasheet Timing Parameters by Speed Bin Timing Parameters by Speed GradeMIN MAX Reset Timing Jitter Notes ZQCorrection TSens x Tdriftrate + VSens x Vdriftrate Timing Parameter Notes18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH0 Physical Dimensions18.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0
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