Samsung M391B5773DH0 Differential Output Slew Rate, Differential output slew rate definition

Page 21

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

12.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOH- diff(AC) for differential signals as shown in below.

[ Table 14 ] Differential Output slew rate definition

Description

Measured

 

Defined by

From

To

 

 

 

 

 

Differential output slew rate for rising edge

VOLdiff(AC)

VOHdiff(AC)

 

VOHdiff(AC)-VOLdiff(AC)

 

Delta TRdiff

 

 

 

 

 

Differential output slew rate for falling edge

VOHdiff(AC)

VOLdiff(AC)

 

VOHdiff(AC)-VOLdiff(AC)

 

Delta TFdiff

 

 

 

 

 

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 15 ] Differential Output slew rate

Parameter

Symbol

Operation

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Units

Voltage

Min

Max

Min

Max

Min

Max

Min

Max

 

 

 

Single ended output slew rate

SRQdiff

1.35V

3.5

12

3.5

12

3.5

12

3.5

12

V/ns

 

 

 

 

 

 

 

 

 

 

1.5V

5

10

5

10

5

10

5

10

V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

diff : Differential Signals For Ron = RZQ/7 setting

VOHdiff(AC)

VTT

VOLdiff(AC)

delta TFdiff

delta TRdiff

Figure 8. Differential output slew rate definition

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Image 21 Contents
Datasheet History Draft Date RevTable Of Contents Address Configuration Key FeaturesDDR3L Unbuffered Dimm Ordering Information Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UnitPin Front Back X72 Dimm Pin Configurations Front side/Back sidePin Description SPD and Thermal Sensor for ECC UDIMMsPin Name Description Input/Output Functional Description Symbol Type FunctionAddress Mirroring Feature Dram Pin Wiring MirroringConnector Pin Dram Pin Rank SCL SDA Event SA0 SA1 SA2 Function Block DiagramD14 Absolute Maximum Ratings Dram Component Operating Temperature RangeAC & DC Operating Conditions Absolute Maximum DC RatingsAC & DC Input Measurement Levels 11.1 AC & DC Logic Input Levels for Single-ended SignalsVIH.DQDC90 Illustration of Vrefdc tolerance and Vref ac-noise limits Vref TolerancesAC and DC Logic Input Levels for Differential Signals Differential Signals Definition35V TBD Time Single-ended Requirements for Differential SignalsCK, DQS Vsel Differential Input Cross Point VoltageSlew rate definition for Differential Input Signals Slew Rate Definition for Single Ended Input SignalsAC & DC Output Measurement Levels Single Ended AC and DC Output LevelsSRQse Single-ended Output Slew RateDifferential output slew rate definition Differential Output Slew RateSymbol Description IDD specification definitionDatasheet IDD Spec Table DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 UnitM391B5773DH0 2GB256Mx72 Module M391B5273DH0 4GB512Mx72 ModuleCZQ Input/Output CapacitanceRefresh Parameters by Device Density Electrical Characteristics and AC timingDDR3-1066 Speed Bins DDR3-1600 Speed Bins CL-nRCD-nRP Speed Bin Table NotesDatasheet Timing Parameters by Speed Bin Timing Parameters by Speed GradeMIN MAX Reset Timing Jitter Notes ZQCorrection TSens x Tdriftrate + VSens x Vdriftrate Timing Parameter Notes18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH0 Physical Dimensions18.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0
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