Samsung M391B5273DH0 Pin Description, SPD and Thermal Sensor for ECC UDIMMs, Pin Name Description

Page 6

Unbuffered DIMM

datasheet

Rev. 1.0

DDR3L SDRAM

5. Pin Description

 

Pin Name

Description

 

Pin Name

Description

 

A0-A14

SDRAM address bus

SCL

I2C serial bus clock for EEPROM

 

BA0-BA2

SDRAM bank select

SDA

I2C serial bus data line for EEPROM

 

 

 

 

 

 

 

 

 

 

 

 

SDRAM row address strobe

SA0-SA2

I2C serial address select for EEPROM

 

RAS

 

 

 

 

 

 

 

 

 

 

 

 

SDRAM column address strobe

 

VDD*

SDRAM core power supply

 

CAS

 

 

 

 

 

 

 

 

 

 

 

SDRAM write enable

 

VDDQ*

SDRAM I/O Driver power supply

 

WE

 

 

 

 

 

 

 

 

 

 

 

 

DIMM Rank Select Lines

 

VREFDQ

SDRAM I/O reference supply

 

S0, S1

 

CKE0,CKE1

SDRAM clock enable lines

 

VREFCA

SDRAM command/address reference supply

 

ODT0, ODT1

On-die termination control lines

 

VSS

Power supply return (ground)

 

DQ0 - DQ63

DIMM memory data bus

 

VDDSPD

Serial EEPROM positive power supply

 

CB0 - CB7

DIMM ECC check bits

NC

Spare Pins(no connect)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQS0 - DQS8

SDRAM data strobes

 

TEST

Used by memory bus analysis tools

 

(positive line of differential pair)

 

(unused on memory DIMMs)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDRAM differential data strobes

 

 

 

 

 

DQS0-DQS8

 

RESET

Set DRAMs Known State

 

(negative line of differential pair)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DM0-DM8

SDRAM data masks/high data strobes

 

 

 

Reserved for optional temperature-sensing hardware

 

 

EVENT

 

(x8-based x72 DIMMs)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CK0, CK1

SDRAM clocks

 

VTT

SDRAM I/O termination supply

 

(positive line of differential pair)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDRAM clocks

 

 

 

 

 

CK0, CK1

 

RFU

Reserved for future use

 

(negative line of differential pair)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE :

*The VDD and VDDQ pins are tied common to a single power-plane on these designs.

**DM8, DQS8 and DQS8 are for ECC UDIMM only.

6. SPD and Thermal Sensor for ECC UDIMMs

On DIMM thermal sensor will provide DRAM temperature readout through a integrated thermal sensor.

 

 

SCL

 

 

 

 

 

 

 

 

 

 

 

SDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EVENT

 

 

 

 

 

WP/EVENT

 

 

 

 

 

 

 

R1

 

 

 

 

 

 

 

 

 

 

 

 

 

SA0

SA1

SA2

 

 

 

 

 

0 Ω

 

 

 

 

 

 

 

 

 

 

R2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SA0

SA1

SA2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE :

1.Raw Cards D (1Rx8 ECC) and E (2Rx8 ECC) support a thermal sensor.

2.When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not. When only the SPD is placed on the module, R2 is placed but R1 is not.

[ Table 1 ] Temperature Sensor Characteristics

Grade

Range

Temperature Sensor Accuracy

Units

NOTE

Min.

Typ.

Max.

 

 

 

 

 

75 < Ta < 95

-

+/- 0.5

+/- 1.0

 

-

 

 

 

 

 

 

 

B

40 < Ta < 125

-

+/- 1.0

+/- 2.0

°C

-

 

 

 

 

 

 

 

 

-20 < Ta < 125

-

+/- 2.0

+/- 3.0

 

-

 

 

 

 

 

 

 

 

Resolution

 

0.25

 

°C /LSB

-

 

 

 

 

 

 

 

 

 

- 6 -

 

 

 

 

Page 5 Page 7
Image 6
Page 5 Page 7
Contents
Datasheet Rev History Draft DateTable Of Contents DDR3L Unbuffered Dimm Ordering Information Key FeaturesAddress Configuration Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 UnitX72 Dimm Pin Configurations Front side/Back side Pin Front BackPin Description SPD and Thermal Sensor for ECC UDIMMsPin Name Description Symbol Type Function Input/Output Functional DescriptionAddress Mirroring Feature Dram Pin Wiring MirroringConnector Pin Dram Pin Rank Function Block Diagram SCL SDA Event SA0 SA1 SA2D14 AC & DC Operating Conditions Dram Component Operating Temperature RangeAbsolute Maximum Ratings Absolute Maximum DC Ratings11.1 AC & DC Logic Input Levels for Single-ended Signals AC & DC Input Measurement LevelsVIH.DQDC90 Vref Tolerances Illustration of Vrefdc tolerance and Vref ac-noise limitsAC and DC Logic Input Levels for Differential Signals Differential Signals Definition35V TBD Single-ended Requirements for Differential Signals TimeDifferential Input Cross Point Voltage CK, DQS VselAC & DC Output Measurement Levels Slew Rate Definition for Single Ended Input SignalsSlew rate definition for Differential Input Signals Single Ended AC and DC Output LevelsSingle-ended Output Slew Rate SRQseDifferential Output Slew Rate Differential output slew rate definitionIDD specification definition Symbol DescriptionDatasheet M391B5773DH0 2GB256Mx72 Module DDR3-1066 DDR3-1333 DDR3-1600 Symbol 11-11-11 UnitIDD Spec Table M391B5273DH0 4GB512Mx72 ModuleInput/Output Capacitance CZQElectrical Characteristics and AC timing Refresh Parameters by Device DensityDDR3-1066 Speed Bins Speed Bin Table Notes DDR3-1600 Speed Bins CL-nRCD-nRPDatasheet Timing Parameters by Speed Grade Timing Parameters by Speed BinMIN MAX Reset Timing Jitter Notes Timing Parameter Notes ZQCorrection TSens x Tdriftrate + VSens x VdriftratePhysical Dimensions 18.1 256Mbx8 based 256Mx72 Module 1 Rank M391B5773DH018.2 256Mbx8 based 512Mx72 Module 2 Ranks M391B5273DH0
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