Texas Instruments TMS3320C5515 manual On-Chip Single-Access RAM Saram, Saram Blocks

Page 18

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Table 1-2. DARAM Blocks

(continued)

 

 

 

 

Memory Block

CPU Byte Address Range

DMA/USB Controller Byte Address Range

 

 

 

 

 

DARAM 6

00 C000h - 00

DFFFh

0001 C000h - 0001

DFFFh

DARAM 7

00 E000h - 00

FFFFh

0001 E000h - 0001

FFFFh

 

 

 

 

 

1.2.1.2On-Chip Single-Access RAM (SARAM)

The SARAM is located at the CPU byte address range 01 0000h - 04FFFFh and is composed of 32 blocks of 4K words each (see Table 1-3). Each SARAM block can perform one access per cycle (one read or one write). SARAM can be accessed by the internal program, data, and DMA buses.

As shown in Table 1-3, the DMA controllers access SARAM at an address offset 0x0008_0000 from the CPU memory byte address space.

Table 1-3. SARAM Blocks

 

 

 

 

DMA/USB Controller Byte Address

Memory Block

CPU Byte Address Range

 

Range

 

 

 

 

 

 

SARAM 0

01 0000h

- 01 1FFFh

0009

0000h

- 0009 1FFFh

SARAM 1

01 2000h

- 01 3FFFh

0009

2000h

- 0009 3FFFh

SARAM 2

01 4000h

- 01 5FFFh

0009

4000h

- 0009 5FFFh

SARAM 3

01 6000h

- 01 7FFFh

0009

6000h

- 0009 7FFFh

SARAM 4

01 8000h

- 01 9FFFh

0009

8000h

- 0009 9FFFh

SARAM 5

01 A000h

- 01 BFFFh

0009 A000h

- 0009 BFFFh

SARAM 6

01 C000h

- 01

DFFFh

0009 C000h

- 0009 DFFFh

SARAM 7

01 E000h - 01 FFFFh

0009 E000h

- 0009 FFFFh

SARAM 8

02 0000h

- 02 1FFFh

000A

0000h

- 000A 1FFFh

SARAM 9

02 2000h

- 02 3FFFh

000A

2000h

- 000A 3FFFh

SARAM 10

02 4000h

- 02 5FFFh

000A

4000h

- 000A 5FFFh

SARAM 11

02 6000h

- 02 7FFFh

000A

6000h

- 000A 7FFFh

SARAM 12

02 8000h

- 02 9FFFh

000A

8000h

- 000A 9FFFh

SARAM 13

02 A000h

- 02 BFFFh

000A A000h

- 000A BFFFh

SARAM 14

02 C000h

- 02

DFFFh

000A C000h

- 000A DFFFh

SARAM 15

02 E000h - 02 FFFFh

000A E000h

- 000A FFFFh

SARAM 16

03 0000h

- 03 1FFFh

000B

0000h

- 000B 1FFFh

SARAM 17

03 2000h

- 03 3FFFh

000B

2000h

- 000B 3FFFh

SARAM 18

03 4000h

- 03 5FFFh

000B

4000h

- 000B 5FFFh

SARAM 19

03 6000h

- 03 7FFFh

000B

6000h

- 000B 7FFFh

SARAM 20

03 8000h

- 03 9FFFh

000B

8000h

- 000B 9FFFh

SARAM 21

03 A000h

- 03 BFFFh

000B A000h

- 000B BFFFh

SARAM 22

03 C000h

- 03 DFFFh

000B C000h

- 000B DFFFh

SARAM 23

03 E000h - 03 FFFFh

000B E000h

- 000B FFFFh

SARAM 24

04 0000h

- 04 1FFFh

000C

0000h

- 000C 1FFFh

SARAM 25

04 2000h

- 04 3FFFh

000C

2000h

- 000C 3FFFh

SARAM 26

04 4000h

- 04 5FFFh

000C

4000h

- 000C 5FFFh

SARAM 27

04 6000h

- 04 7FFFh

000C

6000h

- 000C 7FFFh

SARAM 28

04 8000h

- 04 9FFFh

000C

8000h

- 000C 9FFFh

SARAM 29

04 A000h

- 04 BFFFh

000C A000h

- 000C BFFFh

SARAM 30

04 C000h

- 04 DFFFh

000C C000h

- 000C DFFFh

SARAM 31

04 E000h - 04 FFFFh

000C E000h - 000C FFFFh

 

 

 

 

 

 

 

18 System Control

SPRUFX5A –October 2010 –Revised November 2010

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Block Diagram Functional Block DiagramFFT Hardware Accelerator Using FFT Accelerator ROM routinesCPU Core AddressPower Management PeripheralsSystem Memory Program/Data Memory MapCPU Byte Address Range On-Chip Dual-Access RAM DaramDaram Blocks DaramOn-Chip Single-Access RAM Saram Saram BlocksSaram External Memory On-Chip Single-Access Read-Only Memory SaromSarom Blocks Asynchronous Emif Interface2 I/O Memory Map OverviewDevice Clocking DSP Clocking Diagram Clock Domains Functional Description PLL Output Frequency ConfigurationPowering Down and Powering Up the System PLL Multiplier and DividersClkout Pin SRCBit Field Value Description Clock Generator During Reset ConfigurationDSP Reset Conditions of the System Clock Generator Clock Generator After ResetEntering and Exiting the PLL Mode Register Bits Used in the Bypass ModeSetting the System Clock Frequency In the Bypass Mode Register Bits Used in the PLL ModeFrequency Ranges for Internal Clocks Setting the Output Frequency for the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name 10. PLL Clock Frequency RangesSoftware Steps To Modify Multiplier and Divider Ratios Clock Generator RegistersLock Time 12. Clock Generator RegistersClock Generator Control Register 1 CGCR1 1C20h Clock Generator Control Register 2 CGCR2 1C21hClock Generator Control Register 3 CGCR3 1C22h Clock Generator Control Register 4 CGCR4 1C23hInit Clock Configuration Register 2 CCR2 1C1Fh Clock Configuration Register 1 CCR1 1C1Eh17. Clock Configuration Register 1 CCR1 Field Descriptions 18. Clock Configuration Register 2 CCR2 Field DescriptionsPower Domains 19. Power Management Features20. DSP Power Domains Power Domains DescriptionClock Management CPU Domain Clock Gating Daram21. Idle Configuration Register ICR Field Descriptions Hwai Iporti Mporti Xporti Dporti Idlecfg CpuiHwai Valid Idle Configurations 22. Idle Status Register Istr Field Descriptions23. CPU Clock Domain Idle Requirements To Idle the Following Module/Port Clock Configuration ProcessPeripheral Domain Clock Gating XportMMCSD0CG DMA0CG Uartcg Spicg I2S3CG SysclkdisMMCSD0CG Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg Lcdcg AnaregcgUsbclkstpack UrtclkstpackUrtclkstpreq UsbclkstpreqBit Field Clock Generator Domain Clock GatingUSB Domain Clock Gating EmfclkstpackUsbpwdn Usbsessend Usbvbusdet Usbpllen USB System Control Register Usbscr 1C32h27. USB System Control Register Usbscr Field Descriptions UsbpwdnUsboscbiasdis RTC Domain Clock GatingUsbdatpol UsboscdisStatic Power Management RTC Power Management Register Rtcpmgt 1930hRTC Interrupt Flag Register Rtcintfl 1920h 29. RTC Interrupt Flag Register Rtcintfl Field DescriptionsMode CV DD Voltage Internal Memory Low Power ModesRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h 30. On-Chip Memory Standby Modes21. RAM Sleep Mode Control Register2 0x1C2A DV DDRTC, Ldoi Power Configurations31. Power Configurations IDLE3IDLE2 Procedure IDLE3 Procedure Core Voltage Scaling32. Interrupt Table HEX BytesIFR and IER Registers 33. IFR0 and IER0 Bit DescriptionsRtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 Interrupt Timing34. IFR1 and IER1 Bit Descriptions RtosTimer Interrupt Aggregation Flag Register Tiafr 1C14h Gpio Interrupt Enable and Aggregation Flag RegistersDMA Interrupt Enable and Aggregation Flag Registers Device Identification 35. Die ID RegistersDie ID Register 1 DIEIDR1 1C41h Die ID Register 0 DIEIDR0 1C40h36. Die ID Register 0 DIEIDR0 Field Descriptions 37. Die ID Register 1 DIEIDR1 Field DescriptionsDie ID Register 4 DIEIDR4 1C44h Die ID Register 3 DIEIDR3150 1C43h39. Die ID Register 3 DIEIDR3150 Field Descriptions 40. Die ID Register 4 DIEIDR4 Field DescriptionsDie ID Register 7 DIEIDR7 1C47h Die ID Register 6 DIEIDR6 1C46h42. Die ID Register 6 DIEIDR6 Field Descriptions 43. Die ID Register 7 DIEIDR7 Field DescriptionsDevice Configuration External Bus Selection Register Ebsr44. Ebsr Register Bit Descriptions Field Descriptions A17MODE LDO Control Register 7004hLDO Control A16MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions Rtcpmgt Register Ldocntl Register 46. Ldocntl Register Bit Descriptions Field Descriptions47. LDO Controls Matrix Bgpd Bit Ldopd Bit Usbldoen BitOutput Slew Rate Control Register Osrcr 1C16h ClkoutsrEmifsr S15PD S15PD S14PD S13PD S12PD S11PD S10PDS05PD S04PD S03PD S02PD S01PD S00PD S05PDINT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu Tckpu A20PD A19PD A18PD A17PD A16PD A15PDINT1PU A20PD PD15PDDMA Controller Configuration 52. Channel Synchronization Events for DMA Controllers DMA Configuration RegistersDMA Synchronization Events 53. System Registers Related to the DMA Controllers55. DMA Interrupt Enable Register Dmaier Field Descriptions 54. DMA Interrupt Flag Register Dmaifr Field DescriptionsCH0EVT Peripheral ResetCH1EVT CH3EVTCount Peripheral Software Reset Counter Register Psrcr 1C04hPeripheral Reset Control Register Prcr 1C05h PG4RSTEmif and USB Byte Access PG3RSTBytemode Setting CPU Access to USB Register 60. Effect of Bytemode Bits on Emif Accesses61. Effect of Usbscr Bytemode Bits on USB Access Emif System Control Register Escr 1C33hEmif Clock Divider Register Ecdr 1C26h 63. Emif Clock Divider Register Ecdr Field DescriptionsEdiv Products Applications DSPRfid

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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