Texas Instruments TMS3320C5515 manual Static Power Management

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Power Management

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1.5.4 Static Power Management

1.5.4.1RTC Power Management Register (RTCPMGT) [1930h]

This register enables static power management with power down and wake up register bits as described in the device-specific data sheet and, more generally, below. The RTC power management register (RTCPMGT) is shown in Figure 1-18and described in Table 1-28.

Figure 1-18. RTC Power Management Register (RTCPMGT) [1930h]

15

5

4

3

2

1

0

Reserved

WU_DOUT

WU_DIR

BG_PD

LDO_PD

RTCCLKOUTEN

R-0RW-0RW-0RW-0RW-0RW-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 1-28. RTC Power Management Register (RTCPMGT) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

15-5

Reserved

0

Reserved

 

 

 

 

4

WU_DOUT

 

Wakeup output, active low/Open-drain.

 

 

0

WAKEUP pin driven low.

 

 

1

WAKEUP pin driver is in high impedance.

 

 

 

 

3

WU_DIR

 

Wakeup pin direction control.

 

 

0

WAKEUP pin is configured as input.

 

 

1

WAKEUP pin is configured as output.

 

 

 

NOTE: The WAKEUP pin, when configured as an input, is active high. When it is configured as an

 

 

 

output, it is open-drain and thus it should have an external pull-up and it is active low.

 

 

 

 

2

BG_PD

 

Powerdown control bit for the bandgap, on-chip LDOs, and the analog POR (power on reset)

 

 

 

comparator. This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO), the

 

 

 

Analog POR, and Bandgap reference. BG_PD and LDO_PD are only intended to be used when the

 

 

 

internal LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the

 

 

 

BG_PD and LDO_PD power down mechanisms should not be used since the POR gets powered

 

 

 

down and the POWERGOOD signal would not get generated properly.

 

 

 

After this bit is asserted, the on-chip LDOs, Analog POR, and the Bandgap reference can only be

 

 

 

re-enabled by the WAKEUP pin (being driven HIGH externally) or an enabled RTC alarm or an

 

 

 

enabled RTC periodic event interrupt. Once reenabled, the Bandgap circuit takes about 100 msec to

 

 

 

charge the external 0.1 μF capacitor on the BG_CAP pin via the the internal resistance of

 

 

 

aproxmiately. 320 kΩ.

 

 

0

On-chip LDOs, Analog POR, and Bandgap reference are enabled.

 

 

1

On-chip LDOs, Analog POR, and Bandgap reference are disabled (shutdown).

 

 

 

 

1

LDO_PD

 

On-chip LDOs and Analog POR power down bit. This bit shuts down the on-chip LDOs (ANA_LDO,

 

 

 

DSP_LDO, and USB_LDO) and the Analog POR. BG_PD and LDO_PD are only intended to be

 

 

 

used when the internal LDOs supply power to the chip. If the internal LDOs are bypassed and not

 

 

 

used then the BG_PD and LDO_PD power down mechanisms should not be used since POR gets

 

 

 

powered down and the POWERGOOD signal is not generated properly.

 

 

 

After this bit is asserted, the on-chip LDOs and Analog POR can only be re-enabled by the

 

 

 

WAKEUP pin (being driven HIGH externally) or an enabled RTC alarm or an enabled RTC periodic

 

 

 

event interrupt. This bit keeps the Bandgap reference turned on to allow a faster wake-up time with

 

 

 

the expense power consumption of the Bandgap reference.

 

 

0

On-chip LDOs and Analog POR are enabled.

 

 

1

On-chip LDOs and Analog POR are disabled (shutdown).

 

 

 

 

0

RTCCLKOUTEN

 

Clock-out output enable.

 

 

0

Clock output disabled.

 

 

1

Clock output enabled.

 

 

 

 

46

System Control

SPRUFX5A –October 2010 –Revised November 2010

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Block Diagram Functional Block DiagramFFT Hardware Accelerator Using FFT Accelerator ROM routinesCPU Core AddressPower Management PeripheralsSystem Memory Program/Data Memory MapCPU Byte Address Range On-Chip Dual-Access RAM DaramDaram Blocks DaramSaram Blocks On-Chip Single-Access RAM SaramSaram External Memory On-Chip Single-Access Read-Only Memory SaromSarom Blocks Asynchronous Emif Interface2 I/O Memory Map OverviewDevice Clocking DSP Clocking Diagram Clock Domains Functional Description PLL Output Frequency ConfigurationPowering Down and Powering Up the System PLL Multiplier and DividersSRC Clkout PinBit Field Value Description Clock Generator During Reset ConfigurationDSP Reset Conditions of the System Clock Generator Clock Generator After ResetEntering and Exiting the PLL Mode Register Bits Used in the Bypass ModeSetting the System Clock Frequency In the Bypass Mode Register Bits Used in the PLL ModeFrequency Ranges for Internal Clocks Setting the Output Frequency for the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name 10. PLL Clock Frequency RangesSoftware Steps To Modify Multiplier and Divider Ratios Clock Generator RegistersLock Time 12. Clock Generator RegistersClock Generator Control Register 1 CGCR1 1C20h Clock Generator Control Register 2 CGCR2 1C21hClock Generator Control Register 4 CGCR4 1C23h Clock Generator Control Register 3 CGCR3 1C22hInit Clock Configuration Register 2 CCR2 1C1Fh Clock Configuration Register 1 CCR1 1C1Eh17. Clock Configuration Register 1 CCR1 Field Descriptions 18. Clock Configuration Register 2 CCR2 Field DescriptionsPower Domains 19. Power Management FeaturesPower Domains Description 20. DSP Power DomainsClock Management CPU Domain Clock Gating DaramHwai Iporti Mporti Xporti Dporti Idlecfg Cpui 21. Idle Configuration Register ICR Field DescriptionsHwai 22. Idle Status Register Istr Field Descriptions Valid Idle Configurations23. CPU Clock Domain Idle Requirements To Idle the Following Module/Port Clock Configuration ProcessPeripheral Domain Clock Gating XportMMCSD0CG DMA0CG Uartcg Spicg I2S3CG SysclkdisMMCSD0CG Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg Lcdcg AnaregcgUsbclkstpack UrtclkstpackUrtclkstpreq UsbclkstpreqBit Field Clock Generator Domain Clock GatingUSB Domain Clock Gating EmfclkstpackUsbpwdn Usbsessend Usbvbusdet Usbpllen USB System Control Register Usbscr 1C32h27. USB System Control Register Usbscr Field Descriptions UsbpwdnUsboscbiasdis RTC Domain Clock GatingUsbdatpol UsboscdisStatic Power Management RTC Power Management Register Rtcpmgt 1930hRTC Interrupt Flag Register Rtcintfl 1920h 29. RTC Interrupt Flag Register Rtcintfl Field DescriptionsMode CV DD Voltage Internal Memory Low Power ModesRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h 30. On-Chip Memory Standby Modes21. RAM Sleep Mode Control Register2 0x1C2A DV DDRTC, Ldoi Power Configurations31. Power Configurations IDLE3IDLE2 Procedure IDLE3 Procedure Core Voltage Scaling32. Interrupt Table HEX BytesIFR and IER Registers 33. IFR0 and IER0 Bit DescriptionsRtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 Interrupt Timing34. IFR1 and IER1 Bit Descriptions RtosGpio Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hDMA Interrupt Enable and Aggregation Flag Registers Device Identification 35. Die ID RegistersDie ID Register 1 DIEIDR1 1C41h Die ID Register 0 DIEIDR0 1C40h36. Die ID Register 0 DIEIDR0 Field Descriptions 37. Die ID Register 1 DIEIDR1 Field DescriptionsDie ID Register 4 DIEIDR4 1C44h Die ID Register 3 DIEIDR3150 1C43h39. Die ID Register 3 DIEIDR3150 Field Descriptions 40. Die ID Register 4 DIEIDR4 Field DescriptionsDie ID Register 7 DIEIDR7 1C47h Die ID Register 6 DIEIDR6 1C46h42. Die ID Register 6 DIEIDR6 Field Descriptions 43. Die ID Register 7 DIEIDR7 Field DescriptionsDevice Configuration External Bus Selection Register Ebsr44. Ebsr Register Bit Descriptions Field Descriptions A17MODE LDO Control Register 7004hLDO Control A16MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions Rtcpmgt Register Ldocntl Register 46. Ldocntl Register Bit Descriptions Field Descriptions47. LDO Controls Matrix Bgpd Bit Ldopd Bit Usbldoen BitClkoutsr Output Slew Rate Control Register Osrcr 1C16hEmifsr S15PD S15PD S14PD S13PD S12PD S11PD S10PDS05PD S04PD S03PD S02PD S01PD S00PD S05PDA20PD A19PD A18PD A17PD A16PD A15PD INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuINT1PU A20PD PD15PDDMA Controller Configuration 52. Channel Synchronization Events for DMA Controllers DMA Configuration RegistersDMA Synchronization Events 53. System Registers Related to the DMA Controllers55. DMA Interrupt Enable Register Dmaier Field Descriptions 54. DMA Interrupt Flag Register Dmaifr Field DescriptionsCH0EVT Peripheral ResetCH1EVT CH3EVTCount Peripheral Software Reset Counter Register Psrcr 1C04hPeripheral Reset Control Register Prcr 1C05h PG4RSTEmif and USB Byte Access PG3RSTBytemode Setting CPU Access to USB Register 60. Effect of Bytemode Bits on Emif Accesses61. Effect of Usbscr Bytemode Bits on USB Access Emif System Control Register Escr 1C33h63. Emif Clock Divider Register Ecdr Field Descriptions Emif Clock Divider Register Ecdr 1C26hEdiv DSP Products ApplicationsRfid

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

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Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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