Texas Instruments TMS3320C5515 Frequency Ranges for Internal Clocks, PLL Clock Frequency Ranges

Page 28

System Clock Generatorwww.ti.com

Table 1-9. Clock Generator Control Register Bits Used In PLL Mode (continued)

Register Bit

Role in Bypass Mode

RDRATIO

Specifies the divider ratio of the reference divider.

M

Specify the multiplier value for the PLL.

OUTDIVEN

Determines whether the output divider is bypassed.

ODRATIO

Specifies the divider ratio of the output divider.

 

 

1.4.3.2.3 Frequency Ranges for Internal Clocks

There are specific minimum and maximum frequencies for all the internal clocks. Table 1-10lists the minimum and maximum frequencies for the internal clocks for the DSP.

NOTE: For actual maximum operating frequencies, see the device-specific data sheet.

Table 1-10. PLL Clock Frequency Ranges

 

 

CVDD = 1.05 V

CVDD = 1.3 V

 

Clock Signal Name

MIN

NOM

MAX

MIN

NOM MAX

UNIT

 

 

 

 

 

 

 

 

CLKIN(1)

 

11.289

 

 

11.28

 

MHz

 

 

6

 

 

96

 

 

 

 

12

 

 

12

 

 

 

 

12.288

 

 

12.28

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RTC Clock

 

32.768

 

 

32.76

 

KHz

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLLIN

32.0

 

170

32.0

170

KHz

 

 

 

 

 

 

 

PLLOUT

60

 

120

60

120

MHz

 

 

 

 

 

 

 

 

SYSCLK

0

 

60 or 75

0

 

100 or

MHz

 

 

120

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLL_LOCKTIME

4

 

 

4

 

 

ms

 

 

 

 

 

 

 

 

(1)These CLKIN values are used when the CLK_SEL pin = 1. Bootloader assumes one of these CLKIN frequencies.

1.4.3.2.4Setting the Output Frequency for the PLL MODE

The clock generator output frequency configured based on the settings programmed in the clock generator control registers. The output frequency depends on primarily on three factors: the reference divider value, the PLL multiplier value, and the output divider value (see Figure 1-4). Based on the register settings controlling these divider and multiplier values, you can calculate the frequency of the output clock using the formulas listed in Table 1-5.

Follow these steps to determine the values for the different dividers and multipliers of the system clock generator:

1.With the desired clock frequency in mind, choose a PLLOUT frequency that falls within the range listed in Table 1-10. Keep in mind that you can use the programmable output divider to divide the output frequency of the PLL.

2.Determine the divider ratio for the reference divider that will generate the PLLIN frequency that meets the requirements listed in Table 1-10. When possible, choose a high value for PLLIN to optimize PLL performance. If the DSP is being clocked by the RTC oscillator output, the reference divider must bypassed (set RDBYPASS = 1); PLLIN will be 32.768 kHz.

3.Determine a multiplier value that generates the desired PLLOUT frequency given the equation: multiplier = round( PLLOUT/PLLIN ).

4.Using the multiplier, figure out the values for M (PLL multiplier = M + 4).

28

System Control

SPRUFX5A –October 2010 –Revised November 2010

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Block Diagram Functional Block DiagramUsing FFT Accelerator ROM routines CPU CoreFFT Hardware Accelerator AddressPower Management PeripheralsSystem Memory Program/Data Memory MapOn-Chip Dual-Access RAM Daram Daram BlocksCPU Byte Address Range DaramSaram Blocks On-Chip Single-Access RAM SaramSaram On-Chip Single-Access Read-Only Memory Sarom Sarom BlocksExternal Memory Asynchronous Emif Interface2 I/O Memory Map OverviewDevice Clocking DSP Clocking Diagram Clock Domains PLL Output Frequency Configuration Powering Down and Powering Up the System PLLFunctional Description Multiplier and DividersSRC Clkout PinBit Field Value Description Configuration DSP Reset Conditions of the System Clock GeneratorClock Generator During Reset Clock Generator After ResetRegister Bits Used in the Bypass Mode Setting the System Clock Frequency In the Bypass ModeEntering and Exiting the PLL Mode Register Bits Used in the PLL ModeSetting the Output Frequency for the PLL Mode CV DD = 1.05 CV DD = 1.3 Clock Signal NameFrequency Ranges for Internal Clocks 10. PLL Clock Frequency RangesClock Generator Registers Lock TimeSoftware Steps To Modify Multiplier and Divider Ratios 12. Clock Generator RegistersClock Generator Control Register 1 CGCR1 1C20h Clock Generator Control Register 2 CGCR2 1C21hClock Generator Control Register 4 CGCR4 1C23h Clock Generator Control Register 3 CGCR3 1C22hInit Clock Configuration Register 1 CCR1 1C1Eh 17. Clock Configuration Register 1 CCR1 Field DescriptionsClock Configuration Register 2 CCR2 1C1Fh 18. Clock Configuration Register 2 CCR2 Field DescriptionsPower Domains 19. Power Management FeaturesPower Domains Description 20. DSP Power DomainsClock Management CPU Domain Clock Gating DaramHwai Iporti Mporti Xporti Dporti Idlecfg Cpui 21. Idle Configuration Register ICR Field DescriptionsHwai 22. Idle Status Register Istr Field Descriptions Valid Idle Configurations23. CPU Clock Domain Idle Requirements Clock Configuration Process Peripheral Domain Clock GatingTo Idle the Following Module/Port XportMMCSD0CG DMA0CG Uartcg Spicg I2S3CG SysclkdisMMCSD0CG Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg Lcdcg AnaregcgUrtclkstpack UrtclkstpreqUsbclkstpack UsbclkstpreqClock Generator Domain Clock Gating USB Domain Clock GatingBit Field EmfclkstpackUSB System Control Register Usbscr 1C32h 27. USB System Control Register Usbscr Field DescriptionsUsbpwdn Usbsessend Usbvbusdet Usbpllen UsbpwdnRTC Domain Clock Gating UsbdatpolUsboscbiasdis UsboscdisStatic Power Management RTC Power Management Register Rtcpmgt 1930hRTC Interrupt Flag Register Rtcintfl 1920h 29. RTC Interrupt Flag Register Rtcintfl Field DescriptionsInternal Memory Low Power Modes RAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28hMode CV DD Voltage 30. On-Chip Memory Standby Modes21. RAM Sleep Mode Control Register2 0x1C2A Power Configurations 31. Power ConfigurationsDV DDRTC, Ldoi IDLE3IDLE2 Procedure IDLE3 Procedure Core Voltage Scaling32. Interrupt Table HEX BytesIFR and IER Registers 33. IFR0 and IER0 Bit DescriptionsInterrupt Timing 34. IFR1 and IER1 Bit DescriptionsRtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 RtosGpio Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hDMA Interrupt Enable and Aggregation Flag Registers Device Identification 35. Die ID RegistersDie ID Register 0 DIEIDR0 1C40h 36. Die ID Register 0 DIEIDR0 Field DescriptionsDie ID Register 1 DIEIDR1 1C41h 37. Die ID Register 1 DIEIDR1 Field DescriptionsDie ID Register 3 DIEIDR3150 1C43h 39. Die ID Register 3 DIEIDR3150 Field DescriptionsDie ID Register 4 DIEIDR4 1C44h 40. Die ID Register 4 DIEIDR4 Field DescriptionsDie ID Register 6 DIEIDR6 1C46h 42. Die ID Register 6 DIEIDR6 Field DescriptionsDie ID Register 7 DIEIDR7 1C47h 43. Die ID Register 7 DIEIDR7 Field DescriptionsDevice Configuration External Bus Selection Register Ebsr44. Ebsr Register Bit Descriptions Field Descriptions LDO Control Register 7004h LDO ControlA17MODE A16MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions 46. Ldocntl Register Bit Descriptions Field Descriptions 47. LDO Controls MatrixRtcpmgt Register Ldocntl Register Bgpd Bit Ldopd Bit Usbldoen BitClkoutsr Output Slew Rate Control Register Osrcr 1C16hEmifsr S15PD S14PD S13PD S12PD S11PD S10PD S05PD S04PD S03PD S02PD S01PD S00PDS15PD S05PDA20PD A19PD A18PD A17PD A16PD A15PD INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuINT1PU A20PD PD15PDDMA Controller Configuration DMA Configuration Registers DMA Synchronization Events52. Channel Synchronization Events for DMA Controllers 53. System Registers Related to the DMA Controllers55. DMA Interrupt Enable Register Dmaier Field Descriptions 54. DMA Interrupt Flag Register Dmaifr Field DescriptionsPeripheral Reset CH1EVTCH0EVT CH3EVTPeripheral Software Reset Counter Register Psrcr 1C04h Peripheral Reset Control Register Prcr 1C05hCount PG4RSTEmif and USB Byte Access PG3RST60. Effect of Bytemode Bits on Emif Accesses 61. Effect of Usbscr Bytemode Bits on USB AccessBytemode Setting CPU Access to USB Register Emif System Control Register Escr 1C33h63. Emif Clock Divider Register Ecdr Field Descriptions Emif Clock Divider Register Ecdr 1C26hEdiv DSP Products ApplicationsRfid

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

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Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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