Texas Instruments TMS3320C5515 manual Power Configurations, DV DDRTC, Ldoi, IDLE3, IDLE2

Page 50

Power Management

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1.5.5 Power Configurations

The power-saving features described in the previous sections, such as peripheral clock gating, and on-chip memory power down to name a few, can be combined to form a power configuration. Many different power configurations can be created by enabling and disabling different power domains and clock domains, however, this section defines some basic power configurations that may be useful. These are shown and described in Table 1-31. Please note that there is no single instruction or register that can place the device in these power configurations. Instead, these power configurations are achieved by modifying multiple registers.

NOTE: Before you change the power configuration, make sure that there is a method for the device to exit the power configuration. After exiting a power configuration, your software may have to take additional steps to change the clock and power configuration for other domains.

NOTE: The on-chip Bootloader idles all peripherals and CPU ports at startup. It enables some peripherals as it uses them. Your application code should check the idle configuration of peripherals and CPU ports before using them to be sure these are not idle.

Table 1-31. Power Configurations

 

 

 

Steps to Enter Clock

Available Methods for

Power

Power Domain

 

and Power

Changing/Exiting Clock and

Configuration

State

Clock Domain State

Configuration

Power Configuration

 

 

 

 

 

RTC only mode

DVDDRTC, LDOI,

Only RTC clock is

Set LDO_PD and

A. RTC interrupt

 

and CVDDRTC

running

BG_PD bits in

B. WAKEUP pin

 

powered all others

 

RTCPMGT register

 

 

 

 

powered-down

 

 

 

 

 

 

 

 

IDLE3

All power domains

RTC clock domain

Idle peripheral domain

A. WAKEUP pin

 

on

enabled

 

 

 

 

Other clock domains

Idle CPU domain

B. RTC interrupt

 

 

disabled. Clock

 

 

 

 

generator domain

 

 

 

 

disabled (BYPASS

 

 

 

 

MODE and PLL

 

 

 

 

powerdown).

 

 

 

 

 

PLL in BYPASS MODE

C. External hardware interrupt (INT0

 

 

 

PLL powerdown

or INT1).

 

 

 

Master clock disable

D. Hardware Reset

 

 

 

Execute idle instruction

 

 

 

 

 

 

IDLE2

All power domains

RTC clock domain

Idle peripheral domains

A. WAKEUP pin

 

on

enabled

 

 

 

 

Clock generator domain

Idle CPU domain

B. RTC interrupt

 

 

enabled (PLL_MODE)

 

 

 

 

Other clock domains

Execute idle instruction

C. External hardware interrupt

 

 

disabled

 

(INT0, INT1).

 

 

 

 

D. Any unmasked peripheral

 

 

 

 

interrupt.

 

 

 

 

E. Hardware Reset

 

 

 

 

 

Active

All power domains

All clock domains

Turn on all power

 

 

on

enabled

domains

 

 

 

 

Enable all clock

 

 

 

 

domains

 

 

 

 

 

 

50

System Control

SPRUFX5A –October 2010 –Revised November 2010

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Block Diagram Functional Block DiagramFFT Hardware Accelerator Using FFT Accelerator ROM routinesCPU Core AddressPower Management PeripheralsSystem Memory Program/Data Memory MapCPU Byte Address Range On-Chip Dual-Access RAM DaramDaram Blocks DaramSaram On-Chip Single-Access RAM SaramSaram Blocks External Memory On-Chip Single-Access Read-Only Memory SaromSarom Blocks Asynchronous Emif Interface2 I/O Memory Map OverviewDevice Clocking DSP Clocking Diagram Clock Domains Functional Description PLL Output Frequency ConfigurationPowering Down and Powering Up the System PLL Multiplier and DividersBit Field Value Description Clkout PinSRC Clock Generator During Reset ConfigurationDSP Reset Conditions of the System Clock Generator Clock Generator After ResetEntering and Exiting the PLL Mode Register Bits Used in the Bypass ModeSetting the System Clock Frequency In the Bypass Mode Register Bits Used in the PLL ModeFrequency Ranges for Internal Clocks Setting the Output Frequency for the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name 10. PLL Clock Frequency RangesSoftware Steps To Modify Multiplier and Divider Ratios Clock Generator RegistersLock Time 12. Clock Generator RegistersClock Generator Control Register 1 CGCR1 1C20h Clock Generator Control Register 2 CGCR2 1C21hInit Clock Generator Control Register 3 CGCR3 1C22hClock Generator Control Register 4 CGCR4 1C23h Clock Configuration Register 2 CCR2 1C1Fh Clock Configuration Register 1 CCR1 1C1Eh17. Clock Configuration Register 1 CCR1 Field Descriptions 18. Clock Configuration Register 2 CCR2 Field DescriptionsPower Domains 19. Power Management FeaturesClock Management 20. DSP Power DomainsPower Domains Description CPU Domain Clock Gating DaramHwai 21. Idle Configuration Register ICR Field DescriptionsHwai Iporti Mporti Xporti Dporti Idlecfg Cpui 23. CPU Clock Domain Idle Requirements Valid Idle Configurations22. Idle Status Register Istr Field Descriptions To Idle the Following Module/Port Clock Configuration ProcessPeripheral Domain Clock Gating XportMMCSD0CG DMA0CG Uartcg Spicg I2S3CG SysclkdisMMCSD0CG Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg Lcdcg AnaregcgUsbclkstpack UrtclkstpackUrtclkstpreq UsbclkstpreqBit Field Clock Generator Domain Clock GatingUSB Domain Clock Gating EmfclkstpackUsbpwdn Usbsessend Usbvbusdet Usbpllen USB System Control Register Usbscr 1C32h27. USB System Control Register Usbscr Field Descriptions UsbpwdnUsboscbiasdis RTC Domain Clock GatingUsbdatpol UsboscdisStatic Power Management RTC Power Management Register Rtcpmgt 1930hRTC Interrupt Flag Register Rtcintfl 1920h 29. RTC Interrupt Flag Register Rtcintfl Field DescriptionsMode CV DD Voltage Internal Memory Low Power ModesRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h 30. On-Chip Memory Standby Modes21. RAM Sleep Mode Control Register2 0x1C2A DV DDRTC, Ldoi Power Configurations31. Power Configurations IDLE3IDLE2 Procedure IDLE3 Procedure Core Voltage Scaling32. Interrupt Table HEX BytesIFR and IER Registers 33. IFR0 and IER0 Bit DescriptionsRtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 Interrupt Timing34. IFR1 and IER1 Bit Descriptions RtosDMA Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hGpio Interrupt Enable and Aggregation Flag Registers Device Identification 35. Die ID RegistersDie ID Register 1 DIEIDR1 1C41h Die ID Register 0 DIEIDR0 1C40h36. Die ID Register 0 DIEIDR0 Field Descriptions 37. Die ID Register 1 DIEIDR1 Field DescriptionsDie ID Register 4 DIEIDR4 1C44h Die ID Register 3 DIEIDR3150 1C43h39. Die ID Register 3 DIEIDR3150 Field Descriptions 40. Die ID Register 4 DIEIDR4 Field DescriptionsDie ID Register 7 DIEIDR7 1C47h Die ID Register 6 DIEIDR6 1C46h42. Die ID Register 6 DIEIDR6 Field Descriptions 43. Die ID Register 7 DIEIDR7 Field DescriptionsDevice Configuration External Bus Selection Register Ebsr44. Ebsr Register Bit Descriptions Field Descriptions A17MODE LDO Control Register 7004hLDO Control A16MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions Rtcpmgt Register Ldocntl Register 46. Ldocntl Register Bit Descriptions Field Descriptions47. LDO Controls Matrix Bgpd Bit Ldopd Bit Usbldoen BitEmifsr Output Slew Rate Control Register Osrcr 1C16hClkoutsr S15PD S15PD S14PD S13PD S12PD S11PD S10PDS05PD S04PD S03PD S02PD S01PD S00PD S05PDINT1PU INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuA20PD A19PD A18PD A17PD A16PD A15PD A20PD PD15PDDMA Controller Configuration 52. Channel Synchronization Events for DMA Controllers DMA Configuration RegistersDMA Synchronization Events 53. System Registers Related to the DMA Controllers55. DMA Interrupt Enable Register Dmaier Field Descriptions 54. DMA Interrupt Flag Register Dmaifr Field DescriptionsCH0EVT Peripheral ResetCH1EVT CH3EVTCount Peripheral Software Reset Counter Register Psrcr 1C04hPeripheral Reset Control Register Prcr 1C05h PG4RSTEmif and USB Byte Access PG3RSTBytemode Setting CPU Access to USB Register 60. Effect of Bytemode Bits on Emif Accesses61. Effect of Usbscr Bytemode Bits on USB Access Emif System Control Register Escr 1C33hEdiv Emif Clock Divider Register Ecdr 1C26h63. Emif Clock Divider Register Ecdr Field Descriptions Rfid Products ApplicationsDSP

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

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Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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