Texas Instruments TMS3320C5515 Configuration, DSP Reset Conditions of the System Clock Generator

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System Clock Generator

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1.4.2.4DSP Reset Conditions of the System Clock Generator

The following sections describe the operation of the system clock generator when the DSP is held in reset state and the DSP is removed from its reset state.

1.4.2.4.1 Clock Generator During Reset

During reset, the PLL_PWRDN bit of the clock generator control register 1 (CGCR1) is set to 1, and the PLL does not generate an output clock. Furthermore, the SYSCLKSEL bit of the clock configuration register 2 (CCR2) defaults to 0 (BYPASS MODE), and the system clock (SYSCLK) is driven by either the CLKIN pin or the real-time clock (RTC). See Section 1.4.3.1 for more information on the bypass mode of the clock generator.

1.4.2.4.2 Clock Generator After Reset

After reset, the on-chip bootloader programs the system clock generator based on the input clock selected via the CLK_SEL pin. If CLK_SEL = 0, the bootloader programs the system clock generator and sets the system clock to 12.288 MHz (multiply the 32.768-kHz RTC oscillator clock by 375). If CLK_SEL = 1, the bootloader bypasses the system clock generator altogether and the system clock is driven by the CLKIN pin. In this case, the CLKIN frequency is expected to be 11.2896 MHz, 12.0 MHz, or 12.288 MHz. While the bootloader tries to boot from the USB , the clock generator is programmed to output approximately 36 MHz.

1.4.3 Configuration

1.4.3.1BYPASS MODE

When the system clock generator is in the BYPASS MODE, the clock generator is not used and the system clock (SYSCLK) is driven by either the CLKIN pin or the real-time clock (RTC).

NOTE: In bypass mode, the PLL is not automatically powered down and will still consume power. For maximum power savings, the PLL should be placed in its power-down mode. See Section 1.4.2.2 for more details.

1.4.3.1.1 Entering and Exiting the BYPASS MODE

To enter the bypass mode, write a 0 to the SYSCLKSEL bit in the clock configuration register 2 (CCR2). In bypass mode, the frequency of the system clock (SYSCLK) is determined by the CLK_SEL pin. If CLK_SEL = 0, SYSCLK is driven by the output of the RTC. Otherwise, SYSCLK will be driven by the CLKIN pin.

To exit the BYPASS MODE, ensure the PLL has completed its phase-locking sequence by waiting at least 4 ms and then write a 1 to the SYSCLKSEL bit. The frequency of SYSCLK will then be determined by the multiplier and divider ratios of the PLL System Clock Generator.

If the clock generator is in the PLL MODE and you want to reprogram the PLL or any of the dividers, you must set the clock generator to BYPASS MODE before changing the PLL and divider settings.

Logic within the clock generator ensures that there are no clock glitches during the transition from PLL MODE to BYPASS MODE and vice versa.

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System Control

SPRUFX5A –October 2010 –Revised November 2010

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Block Diagram Functional Block DiagramFFT Hardware Accelerator Using FFT Accelerator ROM routinesCPU Core AddressPower Management PeripheralsSystem Memory Program/Data Memory MapCPU Byte Address Range On-Chip Dual-Access RAM DaramDaram Blocks DaramSaram On-Chip Single-Access RAM SaramSaram Blocks External Memory On-Chip Single-Access Read-Only Memory SaromSarom Blocks Asynchronous Emif Interface2 I/O Memory Map OverviewDevice Clocking DSP Clocking Diagram Clock Domains Functional Description PLL Output Frequency ConfigurationPowering Down and Powering Up the System PLL Multiplier and DividersBit Field Value Description Clkout PinSRC Clock Generator During Reset ConfigurationDSP Reset Conditions of the System Clock Generator Clock Generator After ResetEntering and Exiting the PLL Mode Register Bits Used in the Bypass ModeSetting the System Clock Frequency In the Bypass Mode Register Bits Used in the PLL ModeFrequency Ranges for Internal Clocks Setting the Output Frequency for the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name 10. PLL Clock Frequency RangesSoftware Steps To Modify Multiplier and Divider Ratios Clock Generator RegistersLock Time 12. Clock Generator RegistersClock Generator Control Register 1 CGCR1 1C20h Clock Generator Control Register 2 CGCR2 1C21hInit Clock Generator Control Register 3 CGCR3 1C22hClock Generator Control Register 4 CGCR4 1C23h Clock Configuration Register 2 CCR2 1C1Fh Clock Configuration Register 1 CCR1 1C1Eh17. Clock Configuration Register 1 CCR1 Field Descriptions 18. Clock Configuration Register 2 CCR2 Field DescriptionsPower Domains 19. Power Management FeaturesClock Management 20. DSP Power DomainsPower Domains Description CPU Domain Clock Gating DaramHwai 21. Idle Configuration Register ICR Field DescriptionsHwai Iporti Mporti Xporti Dporti Idlecfg Cpui 23. CPU Clock Domain Idle Requirements Valid Idle Configurations22. Idle Status Register Istr Field Descriptions To Idle the Following Module/Port Clock Configuration ProcessPeripheral Domain Clock Gating XportMMCSD0CG DMA0CG Uartcg Spicg I2S3CG SysclkdisMMCSD0CG Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg Lcdcg AnaregcgUsbclkstpack UrtclkstpackUrtclkstpreq UsbclkstpreqBit Field Clock Generator Domain Clock GatingUSB Domain Clock Gating EmfclkstpackUsbpwdn Usbsessend Usbvbusdet Usbpllen USB System Control Register Usbscr 1C32h27. USB System Control Register Usbscr Field Descriptions UsbpwdnUsboscbiasdis RTC Domain Clock GatingUsbdatpol UsboscdisStatic Power Management RTC Power Management Register Rtcpmgt 1930hRTC Interrupt Flag Register Rtcintfl 1920h 29. RTC Interrupt Flag Register Rtcintfl Field DescriptionsMode CV DD Voltage Internal Memory Low Power ModesRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h 30. On-Chip Memory Standby Modes21. RAM Sleep Mode Control Register2 0x1C2A DV DDRTC, Ldoi Power Configurations31. Power Configurations IDLE3IDLE2 Procedure IDLE3 Procedure Core Voltage Scaling32. Interrupt Table HEX BytesIFR and IER Registers 33. IFR0 and IER0 Bit DescriptionsRtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 Interrupt Timing34. IFR1 and IER1 Bit Descriptions RtosDMA Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hGpio Interrupt Enable and Aggregation Flag Registers Device Identification 35. Die ID RegistersDie ID Register 1 DIEIDR1 1C41h Die ID Register 0 DIEIDR0 1C40h36. Die ID Register 0 DIEIDR0 Field Descriptions 37. Die ID Register 1 DIEIDR1 Field DescriptionsDie ID Register 4 DIEIDR4 1C44h Die ID Register 3 DIEIDR3150 1C43h39. Die ID Register 3 DIEIDR3150 Field Descriptions 40. Die ID Register 4 DIEIDR4 Field DescriptionsDie ID Register 7 DIEIDR7 1C47h Die ID Register 6 DIEIDR6 1C46h42. Die ID Register 6 DIEIDR6 Field Descriptions 43. Die ID Register 7 DIEIDR7 Field DescriptionsDevice Configuration External Bus Selection Register Ebsr44. Ebsr Register Bit Descriptions Field Descriptions A17MODE LDO Control Register 7004hLDO Control A16MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions Rtcpmgt Register Ldocntl Register 46. Ldocntl Register Bit Descriptions Field Descriptions47. LDO Controls Matrix Bgpd Bit Ldopd Bit Usbldoen BitEmifsr Output Slew Rate Control Register Osrcr 1C16hClkoutsr S15PD S15PD S14PD S13PD S12PD S11PD S10PDS05PD S04PD S03PD S02PD S01PD S00PD S05PDINT1PU INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuA20PD A19PD A18PD A17PD A16PD A15PD A20PD PD15PDDMA Controller Configuration 52. Channel Synchronization Events for DMA Controllers DMA Configuration RegistersDMA Synchronization Events 53. System Registers Related to the DMA Controllers55. DMA Interrupt Enable Register Dmaier Field Descriptions 54. DMA Interrupt Flag Register Dmaifr Field DescriptionsCH0EVT Peripheral ResetCH1EVT CH3EVTCount Peripheral Software Reset Counter Register Psrcr 1C04hPeripheral Reset Control Register Prcr 1C05h PG4RSTEmif and USB Byte Access PG3RSTBytemode Setting CPU Access to USB Register 60. Effect of Bytemode Bits on Emif Accesses61. Effect of Usbscr Bytemode Bits on USB Access Emif System Control Register Escr 1C33hEdiv Emif Clock Divider Register Ecdr 1C26h63. Emif Clock Divider Register Ecdr Field Descriptions Rfid Products ApplicationsDSP

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

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Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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