Texas Instruments TMS3320C5515 manual Register Bits Used in the Bypass Mode

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System Clock Generator

1.4.3.1.2 Register Bits Used in the BYPASS MODE

Table 1-7describes the bits of the clock generator control registers that are used in the BYPASS MODE. For detailed descriptions of these bits, see Section 1.4.4.

Table 1-7. Clock Generator Control Register Bits Used In BYPASS MODE

Register Bit

Role in BYPASS MODE

SYSCLKSEL

Allows you to switch to the PLL or BYPASS MODES.

PLL_PWRDN

Allows you to power down the PLL.

 

 

1.4.3.1.3 Setting the System Clock Frequency In the BYPASS MODE

In the BYPASS MODE, the frequency of SYSCLK is determined by the CLK_SEL pin. If CLK_SEL = 0, SYSCLK is driven by the output of the RTC. Otherwise, SYSCLK will be driven by the CLKIN pin.

NOTE: The CLK_SEL pin must be statically tied high or low; it cannot be changed after the device has been powered up.

Table 1-8. Output Frequency in Bypass Mode

CLK_SEL

SYSCLK Source / Frequency

1CLKIN, expected to be one of the following values by the bootloader: 11.2896 MHz, 12.0MHz, or 12.288 MHz

0

RTC clock = 32.768 kHz

The state of the CLK_SEL pin is read via the CLKSELSTAT bit in the CCR2 register.

1.4.3.2PLL MODE

In PLL MODE, the frequency of the input clock signal (CLKREF) can be both multiplied and divided to produce the desired output frequency, and the output clock signal is phase-locked to the input clock signal.

1.4.3.2.1 Entering and Exiting the PLL MODE

To enter the PLL_MODE from BYPASS_MODE, first program the PLL to the desired frequency. You must always ensure the PLL has completed its phase-locking sequence before switching to PLL MODE. This PLL has no lock indicator as such indicators are notoriously unreliable. Instead, a fixed amount of time must be allowed to expire while in BYPASS_MODE to allow the PLL to lock. After 4 msec, write a 1 to the SYSCLKSEL bit in the clock configuration register 2 (CCR2) to set the system clock to the output of the PLL.

Whenever PLL needs to be reprogrammed, first the clock generator must be in bypass mode, and then changed to PLL configuration. After waiting 4 msec, write a 1 to the SYSCLKSEL bit to get into the PLL MODE.

Logic within the clock generator ensures that there are no clock glitches during the transition from BYPASS MODE to PLL MODE and vice versa.

1.4.3.2.2 Register Bits Used in the PLL Mode

Table 1-9describes the bits of the clock generator control registers that are used in the PLL MODE. For detailed descriptions of these bits, see Section 1.4.4.

Table 1-9. Clock Generator Control Register Bits Used In PLL Mode

 

Register Bit

Role in Bypass Mode

 

 

 

 

SYSCLKSEL

Allows you to switch to the PLL or bypass modes.

 

 

 

 

RDBYPASS

Determines whether reference divider should be bypassed or used.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPRUFX5A –October 2010 –Revised November 2010

System Control

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Copyright © 2010, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Functional Block Diagram Block DiagramAddress Using FFT Accelerator ROM routinesCPU Core FFT Hardware AcceleratorPeripherals Power ManagementProgram/Data Memory Map System MemoryDaram On-Chip Dual-Access RAM DaramDaram Blocks CPU Byte Address RangeOn-Chip Single-Access RAM Saram Saram BlocksSaram Asynchronous Emif Interface On-Chip Single-Access Read-Only Memory SaromSarom Blocks External MemoryOverview 2 I/O Memory MapDevice Clocking DSP Clocking Diagram Clock Domains Multiplier and Dividers PLL Output Frequency ConfigurationPowering Down and Powering Up the System PLL Functional DescriptionClkout Pin SRCBit Field Value Description Clock Generator After Reset ConfigurationDSP Reset Conditions of the System Clock Generator Clock Generator During ResetRegister Bits Used in the PLL Mode Register Bits Used in the Bypass ModeSetting the System Clock Frequency In the Bypass Mode Entering and Exiting the PLL Mode10. PLL Clock Frequency Ranges Setting the Output Frequency for the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name Frequency Ranges for Internal Clocks12. Clock Generator Registers Clock Generator RegistersLock Time Software Steps To Modify Multiplier and Divider RatiosClock Generator Control Register 2 CGCR2 1C21h Clock Generator Control Register 1 CGCR1 1C20hClock Generator Control Register 3 CGCR3 1C22h Clock Generator Control Register 4 CGCR4 1C23hInit 18. Clock Configuration Register 2 CCR2 Field Descriptions Clock Configuration Register 1 CCR1 1C1Eh17. Clock Configuration Register 1 CCR1 Field Descriptions Clock Configuration Register 2 CCR2 1C1Fh19. Power Management Features Power Domains20. DSP Power Domains Power Domains DescriptionClock Management Daram CPU Domain Clock Gating21. Idle Configuration Register ICR Field Descriptions Hwai Iporti Mporti Xporti Dporti Idlecfg CpuiHwai Valid Idle Configurations 22. Idle Status Register Istr Field Descriptions23. CPU Clock Domain Idle Requirements Xport Clock Configuration ProcessPeripheral Domain Clock Gating To Idle the Following Module/PortSysclkdis MMCSD0CG DMA0CG Uartcg Spicg I2S3CGMMCSD0CG Anaregcg Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg LcdcgUsbclkstpreq UrtclkstpackUrtclkstpreq UsbclkstpackEmfclkstpack Clock Generator Domain Clock GatingUSB Domain Clock Gating Bit FieldUsbpwdn USB System Control Register Usbscr 1C32h27. USB System Control Register Usbscr Field Descriptions Usbpwdn Usbsessend Usbvbusdet UsbpllenUsboscdis RTC Domain Clock GatingUsbdatpol UsboscbiasdisRTC Power Management Register Rtcpmgt 1930h Static Power Management29. RTC Interrupt Flag Register Rtcintfl Field Descriptions RTC Interrupt Flag Register Rtcintfl 1920h30. On-Chip Memory Standby Modes Internal Memory Low Power ModesRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h Mode CV DD Voltage21. RAM Sleep Mode Control Register2 0x1C2A IDLE3 Power Configurations31. Power Configurations DV DDRTC, LdoiIDLE2 Procedure Core Voltage Scaling IDLE3 ProcedureHEX Bytes 32. Interrupt Table33. IFR0 and IER0 Bit Descriptions IFR and IER RegistersRtos Interrupt Timing34. IFR1 and IER1 Bit Descriptions Rtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3Timer Interrupt Aggregation Flag Register Tiafr 1C14h Gpio Interrupt Enable and Aggregation Flag RegistersDMA Interrupt Enable and Aggregation Flag Registers 35. Die ID Registers Device Identification37. Die ID Register 1 DIEIDR1 Field Descriptions Die ID Register 0 DIEIDR0 1C40h36. Die ID Register 0 DIEIDR0 Field Descriptions Die ID Register 1 DIEIDR1 1C41h40. Die ID Register 4 DIEIDR4 Field Descriptions Die ID Register 3 DIEIDR3150 1C43h39. Die ID Register 3 DIEIDR3150 Field Descriptions Die ID Register 4 DIEIDR4 1C44h43. Die ID Register 7 DIEIDR7 Field Descriptions Die ID Register 6 DIEIDR6 1C46h42. Die ID Register 6 DIEIDR6 Field Descriptions Die ID Register 7 DIEIDR7 1C47hExternal Bus Selection Register Ebsr Device Configuration44. Ebsr Register Bit Descriptions Field Descriptions A16MODE LDO Control Register 7004hLDO Control A17MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions Bgpd Bit Ldopd Bit Usbldoen Bit 46. Ldocntl Register Bit Descriptions Field Descriptions47. LDO Controls Matrix Rtcpmgt Register Ldocntl RegisterOutput Slew Rate Control Register Osrcr 1C16h ClkoutsrEmifsr S05PD S15PD S14PD S13PD S12PD S11PD S10PDS05PD S04PD S03PD S02PD S01PD S00PD S15PDINT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu Tckpu A20PD A19PD A18PD A17PD A16PD A15PDINT1PU PD15PD A20PDDMA Controller Configuration 53. System Registers Related to the DMA Controllers DMA Configuration RegistersDMA Synchronization Events 52. Channel Synchronization Events for DMA Controllers54. DMA Interrupt Flag Register Dmaifr Field Descriptions 55. DMA Interrupt Enable Register Dmaier Field DescriptionsCH3EVT Peripheral ResetCH1EVT CH0EVTPG4RST Peripheral Software Reset Counter Register Psrcr 1C04hPeripheral Reset Control Register Prcr 1C05h CountPG3RST Emif and USB Byte AccessEmif System Control Register Escr 1C33h 60. Effect of Bytemode Bits on Emif Accesses61. Effect of Usbscr Bytemode Bits on USB Access Bytemode Setting CPU Access to USB RegisterEmif Clock Divider Register Ecdr 1C26h 63. Emif Clock Divider Register Ecdr Field DescriptionsEdiv Products Applications DSPRfid

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

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Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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