Texas Instruments TMS3320C5515 manual Clock Configuration Register 1 CCR1 1C1Eh

Page 32

System Clock Generator

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1.4.4.5Clock Configuration Register 1 (CCR1) [1C1Eh]

The clock configuration register 1 (CCR1) is shown in Figure 1-10and described in Table 1-17.

Figure 1-10. Clock Configuration Register 1 (CCR1) [1C1Eh]

15

1

0

Reserved

 

SDCLK_EN

 

 

 

R-0

 

R/W-0

LEGEND: R = Read only; -n= value after reset

Table 1-17. Clock Configuration Register 1 (CCR1) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

15-1

Reserved

0

Reserved. This bit must be kept as 0 during writes to this register.

 

 

 

 

0

SDCLK_EN

 

SDRAM clock enable control. When ON, the EM_SDCLK pin will drive the clock signal at the

 

 

 

SYSCLK frequency if in full_rate mode or at SYSCLK frequency divided by 2 if in half_rate mode.

 

 

 

When OFF, the EM_SDCLK pin will drive low. Transitions from ON to OFF and OFF to ON are not

 

 

 

guaranteed to be glitchless. Therefore, the EMIF should be reset after any change.

 

 

0

EM_SDCLK off (default)

 

 

1

EM_SDCLK on. This bit must be set to 1 before using SDRAM or mSDRAM.

 

 

 

 

1.4.4.6Clock Configuration Register 2 (CCR2) [1C1Fh]

The clock configuration register 2 (CCR2) is shown in Figure 1-11and described in Table 1-18.

Figure 1-11. Clock Configuration Register 2 (CCR2) [1C1Fh]

15

6

5

4

3

2

1

0

Reserved

 

SYSCLKSRC

Reserved

CLKSELSTAT

Reserved

SYSCLKSEL

R-0

 

 

R-0

R/W-0

R-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 1-18. Clock Configuration Register 2 (CCR2) Field Descriptions

Bit

 

Field

Value

Description

 

 

 

 

 

15-6

 

Reserved

0

Reserved.

 

 

 

 

 

5-4

 

SYSCLKSRC

 

System clock source status bits. These read-only bits reflect the source for the system clock. This

 

 

 

 

status register exists to indicate that switching from the PLL BYPASS_MODE to the PLL_MODE

 

 

 

 

was successful or not. Logic exists on the chip to prevent switching to PLL_MODE if the PLL has its

 

 

 

 

PWRDN bit already asserted. However, this circuit does not protect against asserting the PWRDN

 

 

 

 

bit after already in PLL_MODE. Therefore, software must ultimately make sure not to do something

 

 

 

 

that would cause the system clock to be lost.

 

 

 

0

The system clock generator is in bypass mode; SYSCLK is driven by the RTC oscillator output.

 

 

 

1h

The system clock generator is in PLL mode; the RTC oscillator output provides the input clock.

 

 

 

2h

The system clock generator is in bypass mode; SYSCLK is driven by CLKIN.

 

 

 

3h

The system clock generator is in PLL mode; the CLKIN pin provides the input clock.

 

 

 

 

 

3

 

Reserved

0

Reserved. This bit must be written to be 0.

 

 

 

 

 

2

 

CLKSELSTAT

 

CLK_SEL pin status bit. This reflects the state of the CLK_SEL pin.

 

 

 

0

CLK_SEL pin is low (RTC input clock selected).

 

 

 

1

CLK_SEL pin is high (CLKIN input clock selected).

 

 

 

 

 

1

 

Reserved

0

Reserved. This bit must be written to be 0.

 

 

 

 

 

0

 

SYSCLKSEL

 

System clock source select bit. This bit is used to select between the two main clocking modes for

 

 

 

 

the DSP: bypass and PLL mode. In bypass mode, the DSP clock generator is bypassed and the

 

 

 

 

system clock is set to either CLKIN or the RTC output (as determined by the CLKSEL pin). In PLL

 

 

 

 

mode, the system clock is set to the output of the DSP clock generator. Logic in the system clock

 

 

 

 

generator prevents switching from bypass mode to PLL mode if the PLL is powered down.

 

 

 

0

Bypass mode is selected.

 

 

 

1

PLL mode is selected.

 

 

 

 

 

 

 

 

 

 

32

System Control

 

SPRUFX5A –October 2010 –Revised November 2010

 

 

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Block Diagram Functional Block DiagramUsing FFT Accelerator ROM routines CPU CoreFFT Hardware Accelerator AddressPower Management PeripheralsSystem Memory Program/Data Memory MapOn-Chip Dual-Access RAM Daram Daram BlocksCPU Byte Address Range DaramSaram On-Chip Single-Access RAM SaramSaram Blocks On-Chip Single-Access Read-Only Memory Sarom Sarom BlocksExternal Memory Asynchronous Emif Interface2 I/O Memory Map OverviewDevice Clocking DSP Clocking Diagram Clock Domains PLL Output Frequency Configuration Powering Down and Powering Up the System PLLFunctional Description Multiplier and DividersBit Field Value Description Clkout PinSRC Configuration DSP Reset Conditions of the System Clock GeneratorClock Generator During Reset Clock Generator After ResetRegister Bits Used in the Bypass Mode Setting the System Clock Frequency In the Bypass ModeEntering and Exiting the PLL Mode Register Bits Used in the PLL ModeSetting the Output Frequency for the PLL Mode CV DD = 1.05 CV DD = 1.3 Clock Signal NameFrequency Ranges for Internal Clocks 10. PLL Clock Frequency RangesClock Generator Registers Lock TimeSoftware Steps To Modify Multiplier and Divider Ratios 12. Clock Generator RegistersClock Generator Control Register 1 CGCR1 1C20h Clock Generator Control Register 2 CGCR2 1C21hInit Clock Generator Control Register 3 CGCR3 1C22hClock Generator Control Register 4 CGCR4 1C23h Clock Configuration Register 1 CCR1 1C1Eh 17. Clock Configuration Register 1 CCR1 Field DescriptionsClock Configuration Register 2 CCR2 1C1Fh 18. Clock Configuration Register 2 CCR2 Field DescriptionsPower Domains 19. Power Management FeaturesClock Management 20. DSP Power DomainsPower Domains Description CPU Domain Clock Gating DaramHwai 21. Idle Configuration Register ICR Field DescriptionsHwai Iporti Mporti Xporti Dporti Idlecfg Cpui 23. CPU Clock Domain Idle Requirements Valid Idle Configurations22. Idle Status Register Istr Field Descriptions Clock Configuration Process Peripheral Domain Clock GatingTo Idle the Following Module/Port XportMMCSD0CG DMA0CG Uartcg Spicg I2S3CG SysclkdisMMCSD0CG Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg Lcdcg AnaregcgUrtclkstpack UrtclkstpreqUsbclkstpack UsbclkstpreqClock Generator Domain Clock Gating USB Domain Clock GatingBit Field EmfclkstpackUSB System Control Register Usbscr 1C32h 27. USB System Control Register Usbscr Field DescriptionsUsbpwdn Usbsessend Usbvbusdet Usbpllen UsbpwdnRTC Domain Clock Gating UsbdatpolUsboscbiasdis UsboscdisStatic Power Management RTC Power Management Register Rtcpmgt 1930hRTC Interrupt Flag Register Rtcintfl 1920h 29. RTC Interrupt Flag Register Rtcintfl Field DescriptionsInternal Memory Low Power Modes RAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28hMode CV DD Voltage 30. On-Chip Memory Standby Modes21. RAM Sleep Mode Control Register2 0x1C2A Power Configurations 31. Power ConfigurationsDV DDRTC, Ldoi IDLE3IDLE2 Procedure IDLE3 Procedure Core Voltage Scaling32. Interrupt Table HEX BytesIFR and IER Registers 33. IFR0 and IER0 Bit DescriptionsInterrupt Timing 34. IFR1 and IER1 Bit DescriptionsRtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 RtosDMA Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hGpio Interrupt Enable and Aggregation Flag Registers Device Identification 35. Die ID RegistersDie ID Register 0 DIEIDR0 1C40h 36. Die ID Register 0 DIEIDR0 Field DescriptionsDie ID Register 1 DIEIDR1 1C41h 37. Die ID Register 1 DIEIDR1 Field DescriptionsDie ID Register 3 DIEIDR3150 1C43h 39. Die ID Register 3 DIEIDR3150 Field DescriptionsDie ID Register 4 DIEIDR4 1C44h 40. Die ID Register 4 DIEIDR4 Field DescriptionsDie ID Register 6 DIEIDR6 1C46h 42. Die ID Register 6 DIEIDR6 Field DescriptionsDie ID Register 7 DIEIDR7 1C47h 43. Die ID Register 7 DIEIDR7 Field DescriptionsDevice Configuration External Bus Selection Register Ebsr44. Ebsr Register Bit Descriptions Field Descriptions LDO Control Register 7004h LDO ControlA17MODE A16MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions 46. Ldocntl Register Bit Descriptions Field Descriptions 47. LDO Controls MatrixRtcpmgt Register Ldocntl Register Bgpd Bit Ldopd Bit Usbldoen BitEmifsr Output Slew Rate Control Register Osrcr 1C16hClkoutsr S15PD S14PD S13PD S12PD S11PD S10PD S05PD S04PD S03PD S02PD S01PD S00PDS15PD S05PDINT1PU INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuA20PD A19PD A18PD A17PD A16PD A15PD A20PD PD15PDDMA Controller Configuration DMA Configuration Registers DMA Synchronization Events52. Channel Synchronization Events for DMA Controllers 53. System Registers Related to the DMA Controllers55. DMA Interrupt Enable Register Dmaier Field Descriptions 54. DMA Interrupt Flag Register Dmaifr Field DescriptionsPeripheral Reset CH1EVTCH0EVT CH3EVTPeripheral Software Reset Counter Register Psrcr 1C04h Peripheral Reset Control Register Prcr 1C05hCount PG4RSTEmif and USB Byte Access PG3RST60. Effect of Bytemode Bits on Emif Accesses 61. Effect of Usbscr Bytemode Bits on USB AccessBytemode Setting CPU Access to USB Register Emif System Control Register Escr 1C33hEdiv Emif Clock Divider Register Ecdr 1C26h63. Emif Clock Divider Register Ecdr Field Descriptions Rfid Products ApplicationsDSP

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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