Texas Instruments TMS3320C5515 manual MMCSD0CG DMA0CG Uartcg Spicg I2S3CG, Sysclkdis

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Power Management

1.5.3.2.1 Peripheral Clock Gating Configuration Registers (PCGCR1 and PCGCR2) [1C02 - 1C03h]

The peripheral clock gating configuration registers (PCGRC1 and PCGCR2) are used to disable the clocks of the DSP peripherals. In contrast to the idle control register (ICR), these bits take effect within 6 SYSCLK cycles and do not require an idle instruction.

The peripheral clock gating configuration register 1 (PCGCR1) is shown in Figure 1-14and described in Table 1-24.

Figure 1-14. Peripheral Clock Gating Configuration Register 1 (PCGCR1) [1C02h]

15

14

13

12

11

10

9

8

SYSCLKDIS

I2S2CG

TMR2CG

TMR1CG

EMIFCG

TMR0CG

I2S1CG

I2S0CG

 

 

 

 

 

 

 

 

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

MMCSD1CG

I2CCG

Reserved

MMCSD0CG

DMA0CG

UARTCG

SPICG

I2S3CG

 

 

 

 

 

 

 

 

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

 

 

15

SYSCLKDIS

 

System clock disable bit. This bit can be used to turn off the system clock. Setting the WAKEUP pin

 

 

 

high enables the system clock. Since the WAKEUP pin is used to re-enable the system clock, the

 

 

 

 

WAKEUP pin must be low to disable the system clock.

 

 

 

 

 

NOTE Disabling the system clock disables the clock to most parts of the DSP, including the CPU.

 

 

 

0

System clock is active.

 

 

 

 

1

System clock is disabled.

 

 

 

 

 

 

 

14

I2S2CG

 

I2S2 clock gate control bit. This bit is used to enable and disable the I2S2 peripheral clock.

 

 

 

0

Peripheral clock is active.

 

 

 

 

1

Peripheral clock is disabled.

 

 

 

 

 

 

 

13

TMR2CG

 

Timer 2 clock gate control bit. This bit is used to enable and disable the Timer 2 peripheral clock.

 

 

 

0

Peripheral clock is active.

 

 

 

 

1

Peripheral clock is disabled.

 

 

 

 

 

 

 

12

TMR1CG

 

Timer 1 clock gate control bit. This bit is used to enable and disable the Timer 1 peripheral clock.

 

 

 

0

Peripheral clock is active.

 

 

 

 

1

Peripheral clock is disabled.

 

 

 

 

 

 

11

EMIFCG

 

EMIF clock gate control bit. This bit is used to enable and disable the EMIF peripheral clock. NOTE

 

 

 

You must request permission before stopping the EMIF clock through the peripheral clock stop

 

 

 

 

request/acknowledge register (CLKSTOP).

 

 

 

 

0

Peripheral clock is active.

 

 

 

 

1

Peripheral clock is disabled.

 

 

 

 

 

 

 

10

TMR0CG

 

Timer 0 clock gate control bit. This bit is used to enable and disable the Timer 0 peripheral clock.

 

 

 

0

Peripheral clock is active.

 

 

 

 

1

Peripheral clock is disabled.

 

 

 

 

 

 

 

9

I2S1CG

 

I2S1 clock gate control bit. This bit is used to enable and disable the I2S1 peripheral clock.

 

 

 

0

Peripheral clock is active.

 

 

 

 

1

Peripheral clock is disabled.

 

 

 

 

 

 

 

8

I2S0CG

 

I2S0 clock gate control bit. This bit is used to enable and disable the I2S0 peripheral clock.

 

 

 

0

Peripheral clock is active.

 

 

 

 

1

Peripheral clock is disabled.

 

 

 

 

 

 

 

7

MMCSD1CG

 

MMC/SD1 clock gate control bit. This bit is used to enable and disable the MMC/SD1 peripheral

 

 

 

 

clock.

 

 

 

 

0

Peripheral clock is active.

 

 

 

 

1

Peripheral clock is disabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPRUFX5A –October 2010 –Revised November 2010

System Control

39

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Copyright © 2010, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Functional Block Diagram Block DiagramAddress Using FFT Accelerator ROM routinesCPU Core FFT Hardware AcceleratorPeripherals Power ManagementProgram/Data Memory Map System MemoryDaram On-Chip Dual-Access RAM DaramDaram Blocks CPU Byte Address RangeOn-Chip Single-Access RAM Saram Saram BlocksSaram Asynchronous Emif Interface On-Chip Single-Access Read-Only Memory SaromSarom Blocks External MemoryOverview 2 I/O Memory MapDevice Clocking DSP Clocking Diagram Clock Domains Multiplier and Dividers PLL Output Frequency ConfigurationPowering Down and Powering Up the System PLL Functional DescriptionClkout Pin SRCBit Field Value Description Clock Generator After Reset ConfigurationDSP Reset Conditions of the System Clock Generator Clock Generator During ResetRegister Bits Used in the PLL Mode Register Bits Used in the Bypass ModeSetting the System Clock Frequency In the Bypass Mode Entering and Exiting the PLL Mode10. PLL Clock Frequency Ranges Setting the Output Frequency for the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name Frequency Ranges for Internal Clocks12. Clock Generator Registers Clock Generator RegistersLock Time Software Steps To Modify Multiplier and Divider RatiosClock Generator Control Register 2 CGCR2 1C21h Clock Generator Control Register 1 CGCR1 1C20hClock Generator Control Register 3 CGCR3 1C22h Clock Generator Control Register 4 CGCR4 1C23hInit 18. Clock Configuration Register 2 CCR2 Field Descriptions Clock Configuration Register 1 CCR1 1C1Eh17. Clock Configuration Register 1 CCR1 Field Descriptions Clock Configuration Register 2 CCR2 1C1Fh19. Power Management Features Power Domains20. DSP Power Domains Power Domains DescriptionClock Management Daram CPU Domain Clock Gating21. Idle Configuration Register ICR Field Descriptions Hwai Iporti Mporti Xporti Dporti Idlecfg CpuiHwai Valid Idle Configurations 22. Idle Status Register Istr Field Descriptions23. CPU Clock Domain Idle Requirements Xport Clock Configuration ProcessPeripheral Domain Clock Gating To Idle the Following Module/PortSysclkdis MMCSD0CG DMA0CG Uartcg Spicg I2S3CGMMCSD0CG Anaregcg Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg LcdcgUsbclkstpreq UrtclkstpackUrtclkstpreq UsbclkstpackEmfclkstpack Clock Generator Domain Clock GatingUSB Domain Clock Gating Bit FieldUsbpwdn USB System Control Register Usbscr 1C32h27. USB System Control Register Usbscr Field Descriptions Usbpwdn Usbsessend Usbvbusdet UsbpllenUsboscdis RTC Domain Clock GatingUsbdatpol UsboscbiasdisRTC Power Management Register Rtcpmgt 1930h Static Power Management29. RTC Interrupt Flag Register Rtcintfl Field Descriptions RTC Interrupt Flag Register Rtcintfl 1920h30. On-Chip Memory Standby Modes Internal Memory Low Power ModesRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h Mode CV DD Voltage21. RAM Sleep Mode Control Register2 0x1C2A IDLE3 Power Configurations31. Power Configurations DV DDRTC, LdoiIDLE2 Procedure Core Voltage Scaling IDLE3 ProcedureHEX Bytes 32. Interrupt Table33. IFR0 and IER0 Bit Descriptions IFR and IER RegistersRtos Interrupt Timing34. IFR1 and IER1 Bit Descriptions Rtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3Timer Interrupt Aggregation Flag Register Tiafr 1C14h Gpio Interrupt Enable and Aggregation Flag RegistersDMA Interrupt Enable and Aggregation Flag Registers 35. Die ID Registers Device Identification37. Die ID Register 1 DIEIDR1 Field Descriptions Die ID Register 0 DIEIDR0 1C40h36. Die ID Register 0 DIEIDR0 Field Descriptions Die ID Register 1 DIEIDR1 1C41h40. Die ID Register 4 DIEIDR4 Field Descriptions Die ID Register 3 DIEIDR3150 1C43h39. Die ID Register 3 DIEIDR3150 Field Descriptions Die ID Register 4 DIEIDR4 1C44h43. Die ID Register 7 DIEIDR7 Field Descriptions Die ID Register 6 DIEIDR6 1C46h42. Die ID Register 6 DIEIDR6 Field Descriptions Die ID Register 7 DIEIDR7 1C47hExternal Bus Selection Register Ebsr Device Configuration44. Ebsr Register Bit Descriptions Field Descriptions A16MODE LDO Control Register 7004hLDO Control A17MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions Bgpd Bit Ldopd Bit Usbldoen Bit 46. Ldocntl Register Bit Descriptions Field Descriptions47. LDO Controls Matrix Rtcpmgt Register Ldocntl RegisterOutput Slew Rate Control Register Osrcr 1C16h ClkoutsrEmifsr S05PD S15PD S14PD S13PD S12PD S11PD S10PDS05PD S04PD S03PD S02PD S01PD S00PD S15PDINT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu Tckpu A20PD A19PD A18PD A17PD A16PD A15PDINT1PU PD15PD A20PDDMA Controller Configuration 53. System Registers Related to the DMA Controllers DMA Configuration RegistersDMA Synchronization Events 52. Channel Synchronization Events for DMA Controllers54. DMA Interrupt Flag Register Dmaifr Field Descriptions 55. DMA Interrupt Enable Register Dmaier Field DescriptionsCH3EVT Peripheral ResetCH1EVT CH0EVTPG4RST Peripheral Software Reset Counter Register Psrcr 1C04hPeripheral Reset Control Register Prcr 1C05h CountPG3RST Emif and USB Byte AccessEmif System Control Register Escr 1C33h 60. Effect of Bytemode Bits on Emif Accesses61. Effect of Usbscr Bytemode Bits on USB Access Bytemode Setting CPU Access to USB RegisterEmif Clock Divider Register Ecdr 1C26h 63. Emif Clock Divider Register Ecdr Field DescriptionsEdiv Products Applications DSPRfid

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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