Texas Instruments TMS3320C5515 manual Clock Domains, Overview

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System Clock Generator

1.3.2 Clock Domains

The device has many clock domains defined by individually disabled portions of the clock tree structure. Understanding the clock domains and their clock enable/disable control registers is very important for managing power and for ensuring clocks are enabled for domains that are needed. By disabling the clocks and thus the switching current in portions of the chip that are not used, lower dynamic power consumption can be achieved and prolonging battery life.

Figure 1-3shows the clock tree structure with the clock gating represented by the AND gates. Each AND gate shows the controlling register that allows the downstream clock signal to be enabled/disabled. Once disabled most clock domains can be re-enabled, when the associated clock domain logic is needed, via software running on the CPU. But some domains actually stop the clocks to the CPU and therefore software running on the CPU cannot be responsible for re-enabling those clock domains. Other mechanism must exist for restarting those clocks, and the specific cases are listed below:

•The System Clock Generator (PLL) can be powered-down by writing a 1 to PLL_PWRDN bit in the clock generator control register CGCR1. This stops the PLL from oscillating and shuts down its analog circuits. It is important to bypass the System Clock Generator by writing 0 to SYSCLKSEL bit in CCR2 (clock confguration register 2) prior to powering it down, else the CPU will loose its clock and not be able to recover without hardware reset.

NOTE: Failsafe logic exists to prevent selecting the PLL clock if it has been powered down but this logic does not protect against powering down the PLL while it is selected as the system clock source. Therefore, software should always maintain responsibility for bypassing the PLL prior to and whenever it is powered down.

•The SYSCLKDIS bit in PCGCR1 [clock gating control register 1) is the master clock gater. Asserting this bit causes the main system clock, SYSCLK, to stop and, therefore, the CPU and all peripherals no longer receive clocks. The WAKEUP pin, INT0 & INT1 pin, or RTC interrupt can be used to re-enable the clock from this condition.

•The ICR bit in CPUI(clock gating control register) gates clocks to the CPU and uses the CPU’s idle instruction to initiate the clock off mode. Any non-masked interrupt can be used to re-enable the CPU clocks.

1.4System Clock Generator

1.4.1 Overview

The system clock generator (Figure 1-4) features a software-programmable PLL multiplier and several dividers. The clock generator accepts an input clock from the CLKIN pin or the output clock of the real-time clock (RTC) oscillator. The clock generator offers flexibility and convenience by way of software-configurable multiplier and divider to modify the clock rate internally. The resulting clock output, SYSCLK, is passed to the CPU, peripherals, and other modules inside the DSP.

A set of registers are provided for controlling and monitoring the activity of the clock generator. You can write to the SYSCLKSEL bit in CCR2 register to toggle between the two main modes of operation:

•In the BYPASS MODE (see Section 1.4.3.1), the entire clock generator is bypassed, and the frequency of SYSCLK is determined by CLKIN or the RTC oscillator output. Once the PLL is bypassed, the PLL can be powered down to save power.

•In the PLL MODE (see Section 1.4.3.2), the input frequency can be both multiplied and divided to produce the desired SYSCLK frequency, and the SYSCLK signal is phase-locked to the input clock signal (CLKREF).

The clock generator bypass mux (controlled by SYSCLKSEL bit in CCR2 register) is a glitchfree mux, which means that clocks will be switched cleanly and not short cycle pulses when switching among the BYPASS MODE and PLL MODE.

For debug purposes, the CLKOUT pin can be used to see different clocks within the clock generator. For details, see Section 1.4.2.3.

SPRUFX5A –October 2010 –Revised November 2010

System Control

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Functional Block Diagram Block DiagramAddress Using FFT Accelerator ROM routinesCPU Core FFT Hardware AcceleratorPeripherals Power ManagementProgram/Data Memory Map System MemoryDaram On-Chip Dual-Access RAM DaramDaram Blocks CPU Byte Address RangeSaram On-Chip Single-Access RAM SaramSaram Blocks Asynchronous Emif Interface On-Chip Single-Access Read-Only Memory SaromSarom Blocks External MemoryOverview 2 I/O Memory MapDevice Clocking DSP Clocking Diagram Clock Domains Multiplier and Dividers PLL Output Frequency ConfigurationPowering Down and Powering Up the System PLL Functional DescriptionBit Field Value Description Clkout PinSRC Clock Generator After Reset ConfigurationDSP Reset Conditions of the System Clock Generator Clock Generator During ResetRegister Bits Used in the PLL Mode Register Bits Used in the Bypass ModeSetting the System Clock Frequency In the Bypass Mode Entering and Exiting the PLL Mode10. PLL Clock Frequency Ranges Setting the Output Frequency for the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name Frequency Ranges for Internal Clocks12. Clock Generator Registers Clock Generator RegistersLock Time Software Steps To Modify Multiplier and Divider RatiosClock Generator Control Register 2 CGCR2 1C21h Clock Generator Control Register 1 CGCR1 1C20hInit Clock Generator Control Register 3 CGCR3 1C22hClock Generator Control Register 4 CGCR4 1C23h 18. Clock Configuration Register 2 CCR2 Field Descriptions Clock Configuration Register 1 CCR1 1C1Eh17. Clock Configuration Register 1 CCR1 Field Descriptions Clock Configuration Register 2 CCR2 1C1Fh19. Power Management Features Power DomainsClock Management 20. DSP Power DomainsPower Domains Description Daram CPU Domain Clock GatingHwai 21. Idle Configuration Register ICR Field DescriptionsHwai Iporti Mporti Xporti Dporti Idlecfg Cpui 23. CPU Clock Domain Idle Requirements Valid Idle Configurations22. Idle Status Register Istr Field Descriptions Xport Clock Configuration ProcessPeripheral Domain Clock Gating To Idle the Following Module/PortSysclkdis MMCSD0CG DMA0CG Uartcg Spicg I2S3CGMMCSD0CG Anaregcg Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg LcdcgUsbclkstpreq UrtclkstpackUrtclkstpreq UsbclkstpackEmfclkstpack Clock Generator Domain Clock GatingUSB Domain Clock Gating Bit FieldUsbpwdn USB System Control Register Usbscr 1C32h27. USB System Control Register Usbscr Field Descriptions Usbpwdn Usbsessend Usbvbusdet UsbpllenUsboscdis RTC Domain Clock GatingUsbdatpol UsboscbiasdisRTC Power Management Register Rtcpmgt 1930h Static Power Management29. RTC Interrupt Flag Register Rtcintfl Field Descriptions RTC Interrupt Flag Register Rtcintfl 1920h30. On-Chip Memory Standby Modes Internal Memory Low Power ModesRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h Mode CV DD Voltage21. RAM Sleep Mode Control Register2 0x1C2A IDLE3 Power Configurations31. Power Configurations DV DDRTC, LdoiIDLE2 Procedure Core Voltage Scaling IDLE3 ProcedureHEX Bytes 32. Interrupt Table33. IFR0 and IER0 Bit Descriptions IFR and IER RegistersRtos Interrupt Timing34. IFR1 and IER1 Bit Descriptions Rtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3DMA Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hGpio Interrupt Enable and Aggregation Flag Registers 35. Die ID Registers Device Identification37. Die ID Register 1 DIEIDR1 Field Descriptions Die ID Register 0 DIEIDR0 1C40h36. Die ID Register 0 DIEIDR0 Field Descriptions Die ID Register 1 DIEIDR1 1C41h40. Die ID Register 4 DIEIDR4 Field Descriptions Die ID Register 3 DIEIDR3150 1C43h39. Die ID Register 3 DIEIDR3150 Field Descriptions Die ID Register 4 DIEIDR4 1C44h43. Die ID Register 7 DIEIDR7 Field Descriptions Die ID Register 6 DIEIDR6 1C46h42. Die ID Register 6 DIEIDR6 Field Descriptions Die ID Register 7 DIEIDR7 1C47hExternal Bus Selection Register Ebsr Device Configuration44. Ebsr Register Bit Descriptions Field Descriptions A16MODE LDO Control Register 7004hLDO Control A17MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions Bgpd Bit Ldopd Bit Usbldoen Bit 46. Ldocntl Register Bit Descriptions Field Descriptions47. LDO Controls Matrix Rtcpmgt Register Ldocntl RegisterEmifsr Output Slew Rate Control Register Osrcr 1C16hClkoutsr S05PD S15PD S14PD S13PD S12PD S11PD S10PDS05PD S04PD S03PD S02PD S01PD S00PD S15PDINT1PU INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuA20PD A19PD A18PD A17PD A16PD A15PD PD15PD A20PDDMA Controller Configuration 53. System Registers Related to the DMA Controllers DMA Configuration RegistersDMA Synchronization Events 52. Channel Synchronization Events for DMA Controllers54. DMA Interrupt Flag Register Dmaifr Field Descriptions 55. DMA Interrupt Enable Register Dmaier Field DescriptionsCH3EVT Peripheral ResetCH1EVT CH0EVTPG4RST Peripheral Software Reset Counter Register Psrcr 1C04hPeripheral Reset Control Register Prcr 1C05h CountPG3RST Emif and USB Byte AccessEmif System Control Register Escr 1C33h 60. Effect of Bytemode Bits on Emif Accesses61. Effect of Usbscr Bytemode Bits on USB Access Bytemode Setting CPU Access to USB RegisterEdiv Emif Clock Divider Register Ecdr 1C26h63. Emif Clock Divider Register Ecdr Field Descriptions Rfid Products ApplicationsDSP

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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