Texas Instruments TMS3320C5515 manual On-Chip Single-Access Read-Only Memory Sarom, Sarom Blocks

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System Memory

1.2.1.3On-Chip Single-Access Read-Only Memory (SAROM)

The zero-wait-state ROM is located at the CPU byte address range FE 0000h - FF FFFFh. The ROM is composed of four 16K-word blocks, for a total of 128K-bytes of ROM. Each ROM block can perform one access per cycle (one read or one write). ROM can be accessed by the internal program or data buses, but not the DMA buses. The ROM address space can be mapped by software to the external memory or to the internal ROM via the MPNMC bit in the ST3 status register.

The standard device includes a Bootloader program resident in the ROM and the bootloader code is executed immediately after hardware reset. When the MPNMC bit field of the ST3 status register is set through software, the on-chip ROM is disabled and not present in the memory map, and byte address range FE 0000h - FF FFFFh is directed to external memory space (extends CS5 address reach). A hardware reset always clears the MPNMC bit, so it is not possible to disable the ROM at hardware reset. However, the software reset instruction does not affect the MPNMC bit. The ROM can be accessed by the program and data buses. Each SAROM block can perform one word read access per cycle.

Table 1-4. SAROM Blocks

Memory Block

CPU Byte Address Range

CPU Word Address Range

SAROM0

FE 0000h - FE 7FFFh

7F 0000h - 7F 3FFFh

SAROM1

FE 8000h

- FE FFFFh

7F 4000h - 7F 7FFFh

SAROM2

FF 0000h

- FF 7FFFh

7F 8000h - 7F BFFFh

SAROM3

FF 8000h - FF FFFFh

7F C000h - 7F FFFFh

 

 

 

 

1.2.1.4External Memory

The external memory space of the device is located at the byte address range 05 0000h - FF FFFFh. The external memory space is divided into five chip select spaces. The synchronous space is activated by one chip select pin (EM_CS0) or by a pair of chip selects pins (EM_CS0 and EM_CS1). Each asynchronous chip select space has a corresponding chip select pin (called EMIF_CS[2:5]) that is activated during an access to the chip select space.

The external memory interface (EMIF) provides the means for the DSP to access external memories and other devices including: NOR Flash, NAND Flash, SRAM, mSDRAM, and SDRAM (see section 1.5 for limitations). Before accessing external memory, you must configure the EMIF through its registers. For more detail on the EMIF, see the TMS320C5515/14/05/04 DSP External Memory Interface (EMIF) User’s Guide (SPRUGU6).

As described in Section 1.2.1.3, when the MPNMC bit field of the ST3 status register is cleared (default), the byte address range FE 0000h - FF FFFFh is reserved for the on-chip ROM, which decreases the addressable size for EM_CS5.

The EMIF provides a configurable 16-bit (synchronous or asynchronous) or 8-bit (asynchronous only) data bus, an address bus width of up to 21-bits, and five dedicated chip selects, along with memory control signals. To maximize power savings, the I/O pins of the EMIF can be operated at lower voltage independently of other I/O pins on the DSP. Further power savings may be achieved by setting the EMIF I/O pins to have slow slew rate, as described in Section 1.7.3.4.

1.2.1.4.1 Asynchronous EMIF Interface

The EMIF provides a configurable 16- or 8-bit data bus with address bus width of up to 21-bits, and six dedicated chip selects, along with memory control signals. The cycle timings of the asynchronous interface are fully programmable, allowing for access to a wide range of devices including NAND flash, NOR flash, and SRAM as well as other asynchronous devices such as a TI DSP HPI interface. In NAND mode, the asynchronous interface supports 1-bit ECC for 8- and 16-bit NAND flash and 4-bit ECC for 8-bit NAND flash.

1.2.1.5Synchronous EMIF Interface

The EMIF provides a 16-bit data bus with one or two dedicated chip selects for mSDRAM. Non-mobile SDRAM can be supported under certain circumstances. The C5515 always uses a mobile SDRAM initialization command sequence, but it is able to support SDRAM memories that ignore the BA0 and BA1

SPRUFX5A –October 2010 –Revised November 2010

System Control

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Copyright © 2010, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Functional Block Diagram Block DiagramAddress Using FFT Accelerator ROM routinesCPU Core FFT Hardware AcceleratorPeripherals Power ManagementProgram/Data Memory Map System MemoryDaram On-Chip Dual-Access RAM DaramDaram Blocks CPU Byte Address RangeSaram Blocks On-Chip Single-Access RAM SaramSaram Asynchronous Emif Interface On-Chip Single-Access Read-Only Memory SaromSarom Blocks External MemoryOverview 2 I/O Memory MapDevice Clocking DSP Clocking Diagram Clock Domains Multiplier and Dividers PLL Output Frequency ConfigurationPowering Down and Powering Up the System PLL Functional DescriptionSRC Clkout PinBit Field Value Description Clock Generator After Reset ConfigurationDSP Reset Conditions of the System Clock Generator Clock Generator During ResetRegister Bits Used in the PLL Mode Register Bits Used in the Bypass ModeSetting the System Clock Frequency In the Bypass Mode Entering and Exiting the PLL Mode10. PLL Clock Frequency Ranges Setting the Output Frequency for the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name Frequency Ranges for Internal Clocks12. Clock Generator Registers Clock Generator RegistersLock Time Software Steps To Modify Multiplier and Divider RatiosClock Generator Control Register 2 CGCR2 1C21h Clock Generator Control Register 1 CGCR1 1C20hClock Generator Control Register 4 CGCR4 1C23h Clock Generator Control Register 3 CGCR3 1C22hInit 18. Clock Configuration Register 2 CCR2 Field Descriptions Clock Configuration Register 1 CCR1 1C1Eh17. Clock Configuration Register 1 CCR1 Field Descriptions Clock Configuration Register 2 CCR2 1C1Fh19. Power Management Features Power DomainsPower Domains Description 20. DSP Power DomainsClock Management Daram CPU Domain Clock GatingHwai Iporti Mporti Xporti Dporti Idlecfg Cpui 21. Idle Configuration Register ICR Field DescriptionsHwai 22. Idle Status Register Istr Field Descriptions Valid Idle Configurations23. CPU Clock Domain Idle Requirements Xport Clock Configuration ProcessPeripheral Domain Clock Gating To Idle the Following Module/PortSysclkdis MMCSD0CG DMA0CG Uartcg Spicg I2S3CGMMCSD0CG Anaregcg Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg LcdcgUsbclkstpreq UrtclkstpackUrtclkstpreq UsbclkstpackEmfclkstpack Clock Generator Domain Clock GatingUSB Domain Clock Gating Bit FieldUsbpwdn USB System Control Register Usbscr 1C32h27. USB System Control Register Usbscr Field Descriptions Usbpwdn Usbsessend Usbvbusdet UsbpllenUsboscdis RTC Domain Clock GatingUsbdatpol UsboscbiasdisRTC Power Management Register Rtcpmgt 1930h Static Power Management29. RTC Interrupt Flag Register Rtcintfl Field Descriptions RTC Interrupt Flag Register Rtcintfl 1920h30. On-Chip Memory Standby Modes Internal Memory Low Power ModesRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h Mode CV DD Voltage21. RAM Sleep Mode Control Register2 0x1C2A IDLE3 Power Configurations31. Power Configurations DV DDRTC, LdoiIDLE2 Procedure Core Voltage Scaling IDLE3 ProcedureHEX Bytes 32. Interrupt Table33. IFR0 and IER0 Bit Descriptions IFR and IER RegistersRtos Interrupt Timing34. IFR1 and IER1 Bit Descriptions Rtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3Gpio Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hDMA Interrupt Enable and Aggregation Flag Registers 35. Die ID Registers Device Identification37. Die ID Register 1 DIEIDR1 Field Descriptions Die ID Register 0 DIEIDR0 1C40h36. Die ID Register 0 DIEIDR0 Field Descriptions Die ID Register 1 DIEIDR1 1C41h40. Die ID Register 4 DIEIDR4 Field Descriptions Die ID Register 3 DIEIDR3150 1C43h39. Die ID Register 3 DIEIDR3150 Field Descriptions Die ID Register 4 DIEIDR4 1C44h43. Die ID Register 7 DIEIDR7 Field Descriptions Die ID Register 6 DIEIDR6 1C46h42. Die ID Register 6 DIEIDR6 Field Descriptions Die ID Register 7 DIEIDR7 1C47hExternal Bus Selection Register Ebsr Device Configuration44. Ebsr Register Bit Descriptions Field Descriptions A16MODE LDO Control Register 7004hLDO Control A17MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions Bgpd Bit Ldopd Bit Usbldoen Bit 46. Ldocntl Register Bit Descriptions Field Descriptions47. LDO Controls Matrix Rtcpmgt Register Ldocntl RegisterClkoutsr Output Slew Rate Control Register Osrcr 1C16hEmifsr S05PD S15PD S14PD S13PD S12PD S11PD S10PDS05PD S04PD S03PD S02PD S01PD S00PD S15PDA20PD A19PD A18PD A17PD A16PD A15PD INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuINT1PU PD15PD A20PDDMA Controller Configuration 53. System Registers Related to the DMA Controllers DMA Configuration RegistersDMA Synchronization Events 52. Channel Synchronization Events for DMA Controllers54. DMA Interrupt Flag Register Dmaifr Field Descriptions 55. DMA Interrupt Enable Register Dmaier Field DescriptionsCH3EVT Peripheral ResetCH1EVT CH0EVTPG4RST Peripheral Software Reset Counter Register Psrcr 1C04hPeripheral Reset Control Register Prcr 1C05h CountPG3RST Emif and USB Byte AccessEmif System Control Register Escr 1C33h 60. Effect of Bytemode Bits on Emif Accesses61. Effect of Usbscr Bytemode Bits on USB Access Bytemode Setting CPU Access to USB Register63. Emif Clock Divider Register Ecdr Field Descriptions Emif Clock Divider Register Ecdr 1C26hEdiv DSP Products ApplicationsRfid

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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