Texas Instruments TMS3320C5515 Clock Configuration Process, Peripheral Domain Clock Gating, Xport

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Table 1-23. CPU Clock Domain Idle Requirements (continued)

To Idle the Following Module/Port

Requirements Before Going to Idle

XPORT

CPU CPUI must also be set.

DPORT

1.5.3.1.3 Clock Configuration Process

The clock configuration indicates which portions of the CPU clock domain will be idle, and which will be active. The basic steps to the clock configuration process are:

1.To idle MPORT, DMA controller, LCD DMA, and USB CDMA must not be accessing SARMA or DARAM. If any DMA is in active, wait for completion of the DMA transfer.

2.Write the desired configuration to the idle configuration register (ICR). Make sure that you use a valid idle configuration (see Section 1.5.3.1.2).

3.Apply the new idle configuration by executing the IDLE instruction. The content of ICR is copied to the idle status register (ISTR). The bits of ISTR are then propagated through the CPU domain system to enable or disable the specified clocks. If the CPU domain was idled, then program execution will stop immediately after the idle instruction. If the CPU domain was not idled, then program execution will continue past the idle instruction but the appropriate domains will be idle.

The IDLE instruction cannot be executed in parallel with another instruction.

The CPU, DPORT, XPORT, and IPORT domains are enabled automatically by any unmasked interrupts. There is a logic in the DSP core that enables CPU, DPORT, XPORT, and IPORT (clears the bits 0, 5, 6, and 8 of the ISTR register) asynchronously upon detecting an interrupt signal. Therefore, when an unmasked interrupt signal reaches the DSP core, these domains are un-idled automatically. Once the CPU is enabled, it takes 3 CPU cycles to detect the interrupt in the IFR. Note that HWA and MPORT have to be manually enabled after being disabled.

1.5.3.2Peripheral Domain Clock Gating

The peripheral clock gating allows software to disable clocks to the DSP peripherals, in order to reduce the peripheral'sactive power consumption to zero. Aside from the analog logic, the DSP is designed in static CMOS; thus, when a peripheral clock stops, the peripheral'sstate is preserved, and no active current is consumed. When the clock is restarted the peripheral resumes operating from the stopping point.

NOTE: Stopping clocks to a peripheral only affects active power consumption; it does not affect leakage power consumption.

If a peripheral'sclock is stopped while being accessed, the access may not occur completely, and could potentially lock-up the device. To avoid this issue, some peripherals have a clock stop request and acknowledge protocol that allows software to ask the peripheral when it is safe to stop the clocks. This is described further in Section 1.5.3.2.2. For the peripherals that do not have the request/acknowledge protocol, the user must ensure that all of the transactions to the peripheral are finished prior to stopping the clocks.

The procedure to turn peripheral clocks on/off is described in Section 1.5.3.2.3.

Some peripherals provide additional power saving features by clock gating components within its peripheral boundary. See the peripheral-specific user'sguide for more details on these additional power saving features.

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System Control

SPRUFX5A –October 2010 –Revised November 2010

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Block Diagram Functional Block DiagramFFT Hardware Accelerator Using FFT Accelerator ROM routinesCPU Core AddressPower Management PeripheralsSystem Memory Program/Data Memory MapCPU Byte Address Range On-Chip Dual-Access RAM DaramDaram Blocks DaramSaram On-Chip Single-Access RAM SaramSaram Blocks External Memory On-Chip Single-Access Read-Only Memory SaromSarom Blocks Asynchronous Emif Interface2 I/O Memory Map OverviewDevice Clocking DSP Clocking Diagram Clock Domains Functional Description PLL Output Frequency ConfigurationPowering Down and Powering Up the System PLL Multiplier and DividersBit Field Value Description Clkout PinSRC Clock Generator During Reset ConfigurationDSP Reset Conditions of the System Clock Generator Clock Generator After ResetEntering and Exiting the PLL Mode Register Bits Used in the Bypass ModeSetting the System Clock Frequency In the Bypass Mode Register Bits Used in the PLL ModeFrequency Ranges for Internal Clocks Setting the Output Frequency for the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name 10. PLL Clock Frequency RangesSoftware Steps To Modify Multiplier and Divider Ratios Clock Generator RegistersLock Time 12. Clock Generator RegistersClock Generator Control Register 1 CGCR1 1C20h Clock Generator Control Register 2 CGCR2 1C21hInit Clock Generator Control Register 3 CGCR3 1C22hClock Generator Control Register 4 CGCR4 1C23h Clock Configuration Register 2 CCR2 1C1Fh Clock Configuration Register 1 CCR1 1C1Eh17. Clock Configuration Register 1 CCR1 Field Descriptions 18. Clock Configuration Register 2 CCR2 Field DescriptionsPower Domains 19. Power Management FeaturesClock Management 20. DSP Power DomainsPower Domains Description CPU Domain Clock Gating DaramHwai 21. Idle Configuration Register ICR Field DescriptionsHwai Iporti Mporti Xporti Dporti Idlecfg Cpui 23. CPU Clock Domain Idle Requirements Valid Idle Configurations22. Idle Status Register Istr Field Descriptions To Idle the Following Module/Port Clock Configuration ProcessPeripheral Domain Clock Gating XportMMCSD0CG DMA0CG Uartcg Spicg I2S3CG SysclkdisMMCSD0CG Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg Lcdcg AnaregcgUsbclkstpack UrtclkstpackUrtclkstpreq UsbclkstpreqBit Field Clock Generator Domain Clock GatingUSB Domain Clock Gating EmfclkstpackUsbpwdn Usbsessend Usbvbusdet Usbpllen USB System Control Register Usbscr 1C32h27. USB System Control Register Usbscr Field Descriptions UsbpwdnUsboscbiasdis RTC Domain Clock GatingUsbdatpol UsboscdisStatic Power Management RTC Power Management Register Rtcpmgt 1930hRTC Interrupt Flag Register Rtcintfl 1920h 29. RTC Interrupt Flag Register Rtcintfl Field DescriptionsMode CV DD Voltage Internal Memory Low Power ModesRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h 30. On-Chip Memory Standby Modes21. RAM Sleep Mode Control Register2 0x1C2A DV DDRTC, Ldoi Power Configurations31. Power Configurations IDLE3IDLE2 Procedure IDLE3 Procedure Core Voltage Scaling32. Interrupt Table HEX BytesIFR and IER Registers 33. IFR0 and IER0 Bit DescriptionsRtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 Interrupt Timing34. IFR1 and IER1 Bit Descriptions RtosDMA Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hGpio Interrupt Enable and Aggregation Flag Registers Device Identification 35. Die ID RegistersDie ID Register 1 DIEIDR1 1C41h Die ID Register 0 DIEIDR0 1C40h36. Die ID Register 0 DIEIDR0 Field Descriptions 37. Die ID Register 1 DIEIDR1 Field DescriptionsDie ID Register 4 DIEIDR4 1C44h Die ID Register 3 DIEIDR3150 1C43h39. Die ID Register 3 DIEIDR3150 Field Descriptions 40. Die ID Register 4 DIEIDR4 Field DescriptionsDie ID Register 7 DIEIDR7 1C47h Die ID Register 6 DIEIDR6 1C46h42. Die ID Register 6 DIEIDR6 Field Descriptions 43. Die ID Register 7 DIEIDR7 Field DescriptionsDevice Configuration External Bus Selection Register Ebsr44. Ebsr Register Bit Descriptions Field Descriptions A17MODE LDO Control Register 7004hLDO Control A16MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions Rtcpmgt Register Ldocntl Register 46. Ldocntl Register Bit Descriptions Field Descriptions47. LDO Controls Matrix Bgpd Bit Ldopd Bit Usbldoen BitEmifsr Output Slew Rate Control Register Osrcr 1C16hClkoutsr S15PD S15PD S14PD S13PD S12PD S11PD S10PDS05PD S04PD S03PD S02PD S01PD S00PD S05PDINT1PU INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuA20PD A19PD A18PD A17PD A16PD A15PD A20PD PD15PDDMA Controller Configuration 52. Channel Synchronization Events for DMA Controllers DMA Configuration RegistersDMA Synchronization Events 53. System Registers Related to the DMA Controllers55. DMA Interrupt Enable Register Dmaier Field Descriptions 54. DMA Interrupt Flag Register Dmaifr Field DescriptionsCH0EVT Peripheral ResetCH1EVT CH3EVTCount Peripheral Software Reset Counter Register Psrcr 1C04hPeripheral Reset Control Register Prcr 1C05h PG4RSTEmif and USB Byte Access PG3RSTBytemode Setting CPU Access to USB Register 60. Effect of Bytemode Bits on Emif Accesses61. Effect of Usbscr Bytemode Bits on USB Access Emif System Control Register Escr 1C33hEdiv Emif Clock Divider Register Ecdr 1C26h63. Emif Clock Divider Register Ecdr Field Descriptions Rfid Products ApplicationsDSP

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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