Texas Instruments TMS3320C5515 manual Idle Status Register Istr Field Descriptions

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Figure 1-13. Idle Status Register (ISTR) [0002h]

15

 

 

 

 

10

9

8

 

 

Reserved

 

 

HWAIS

IPORTIS

 

 

 

 

 

 

 

 

 

R-0

 

 

R-0

R-0

7

6

5

 

4

 

1

0

 

 

 

 

 

 

 

 

MPORTIS

XPORTIS

DPORTIS

 

Reserved

 

 

CPUIS

 

 

 

 

 

 

 

 

R-0

R-0

R-0

R-0

 

 

R-0

LEGEND: R = Read only; -n= value after reset

Table 1-22. Idle Status Register (ISTR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

15-10

Reserved

0

Reserved.

 

 

 

 

9

HWAIS

 

FFT hardware accelerator idle status bit.

 

 

0

Hardware accelerator is active.

 

 

1

Hardware accelerator is disabled.

 

 

 

 

8

IPORTIS

 

Instruction port idle status bit. The IPORT is used for all external memory instruction accesses.

 

 

0

IPORT is active.

 

 

1

IPORT is disabled.

 

 

 

 

7

MPORTIS

 

Memory port idle status bit. The memory port is used for all DMA, LCD DMA, and USB CDMA

 

 

 

transactions into on-chip memory.

 

 

0

MPORT is active.

 

 

1

MPORT is disabled.

 

 

 

 

6

XPORTIS

 

I/O port idle status bit. The XPORT is used for all CPU I/O memory transactions.

 

 

0

XPORT is active.

 

 

1

XPORT is disabled.

 

 

 

 

5

DPORTIS

 

Data port idle status bit. The data port is used for all CPU external memory data accesses.

 

 

0

DPORT is active.

 

 

1

DPORT is disabled.

 

 

 

 

4-1

Reserved

0

Reserved.

 

 

 

 

0

CPUIS

 

CPU idle status bit.

 

 

0

CPU is active.

 

 

1

CPU is disabled.

 

 

 

 

1.5.3.1.2 Valid Idle Configurations

Not all of the values that you can write to the idle configuration register (ICR) provide valid idle configurations. The valid configurations are limited by dependencies within the system. For example, the IDLECFG bits 1, 2 and 3 of ICR must always be set to 1, and bit 4 must always be cleared to 0. As another example, the XPORT cannot be idled unless the CPU is also idled. Before any part of the CPU domain is idled, you must observe the requirements outlined in Section 1.5.3.2.

A bus error will be generated (BERR = 1 in IFR1) if you execute the idle instruction under any of the following conditions and the idle command will not take effect:

1.If you fail to set IDLECFG = 0111 while setting any of these bits: DPORTI, XPORTI, IPORTI or

MPORTI.

2.If you set DPORTI, XPORTI, or IPORTI without also setting CPUI.

Table 1-23. CPU Clock Domain Idle Requirements

 

To Idle the Following Module/Port

Requirements Before Going to Idle

 

 

 

 

 

 

CPU

No requirements.

 

 

FFT Hardware Accelerator

No requirements.

 

 

MPORT

DMA controllers, LCD, and USB CDMA must not be accessing DARAM or SARAM.

 

 

 

 

 

 

 

 

SPRUFX5A –October 2010 –Revised November 2010

System Control 37

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Copyright © 2010, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Functional Block Diagram Block DiagramCPU Core Using FFT Accelerator ROM routinesFFT Hardware Accelerator AddressPeripherals Power ManagementProgram/Data Memory Map System MemoryDaram Blocks On-Chip Dual-Access RAM DaramCPU Byte Address Range DaramSaram Blocks On-Chip Single-Access RAM SaramSaram Sarom Blocks On-Chip Single-Access Read-Only Memory SaromExternal Memory Asynchronous Emif InterfaceOverview 2 I/O Memory MapDevice Clocking DSP Clocking Diagram Clock Domains Powering Down and Powering Up the System PLL PLL Output Frequency ConfigurationFunctional Description Multiplier and DividersSRC Clkout PinBit Field Value Description DSP Reset Conditions of the System Clock Generator ConfigurationClock Generator During Reset Clock Generator After ResetSetting the System Clock Frequency In the Bypass Mode Register Bits Used in the Bypass ModeEntering and Exiting the PLL Mode Register Bits Used in the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name Setting the Output Frequency for the PLL ModeFrequency Ranges for Internal Clocks 10. PLL Clock Frequency RangesLock Time Clock Generator RegistersSoftware Steps To Modify Multiplier and Divider Ratios 12. Clock Generator RegistersClock Generator Control Register 2 CGCR2 1C21h Clock Generator Control Register 1 CGCR1 1C20hClock Generator Control Register 4 CGCR4 1C23h Clock Generator Control Register 3 CGCR3 1C22hInit 17. Clock Configuration Register 1 CCR1 Field Descriptions Clock Configuration Register 1 CCR1 1C1EhClock Configuration Register 2 CCR2 1C1Fh 18. Clock Configuration Register 2 CCR2 Field Descriptions19. Power Management Features Power DomainsPower Domains Description 20. DSP Power DomainsClock Management Daram CPU Domain Clock GatingHwai Iporti Mporti Xporti Dporti Idlecfg Cpui 21. Idle Configuration Register ICR Field DescriptionsHwai 22. Idle Status Register Istr Field Descriptions Valid Idle Configurations23. CPU Clock Domain Idle Requirements Peripheral Domain Clock Gating Clock Configuration ProcessTo Idle the Following Module/Port XportSysclkdis MMCSD0CG DMA0CG Uartcg Spicg I2S3CGMMCSD0CG Anaregcg Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg LcdcgUrtclkstpreq UrtclkstpackUsbclkstpack UsbclkstpreqUSB Domain Clock Gating Clock Generator Domain Clock GatingBit Field Emfclkstpack27. USB System Control Register Usbscr Field Descriptions USB System Control Register Usbscr 1C32hUsbpwdn Usbsessend Usbvbusdet Usbpllen UsbpwdnUsbdatpol RTC Domain Clock GatingUsboscbiasdis UsboscdisRTC Power Management Register Rtcpmgt 1930h Static Power Management29. RTC Interrupt Flag Register Rtcintfl Field Descriptions RTC Interrupt Flag Register Rtcintfl 1920hRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h Internal Memory Low Power ModesMode CV DD Voltage 30. On-Chip Memory Standby Modes21. RAM Sleep Mode Control Register2 0x1C2A 31. Power Configurations Power ConfigurationsDV DDRTC, Ldoi IDLE3IDLE2 Procedure Core Voltage Scaling IDLE3 ProcedureHEX Bytes 32. Interrupt Table33. IFR0 and IER0 Bit Descriptions IFR and IER Registers34. IFR1 and IER1 Bit Descriptions Interrupt TimingRtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 RtosGpio Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hDMA Interrupt Enable and Aggregation Flag Registers 35. Die ID Registers Device Identification36. Die ID Register 0 DIEIDR0 Field Descriptions Die ID Register 0 DIEIDR0 1C40hDie ID Register 1 DIEIDR1 1C41h 37. Die ID Register 1 DIEIDR1 Field Descriptions39. Die ID Register 3 DIEIDR3150 Field Descriptions Die ID Register 3 DIEIDR3150 1C43hDie ID Register 4 DIEIDR4 1C44h 40. Die ID Register 4 DIEIDR4 Field Descriptions42. Die ID Register 6 DIEIDR6 Field Descriptions Die ID Register 6 DIEIDR6 1C46hDie ID Register 7 DIEIDR7 1C47h 43. Die ID Register 7 DIEIDR7 Field DescriptionsExternal Bus Selection Register Ebsr Device Configuration44. Ebsr Register Bit Descriptions Field Descriptions LDO Control LDO Control Register 7004hA17MODE A16MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions 47. LDO Controls Matrix 46. Ldocntl Register Bit Descriptions Field DescriptionsRtcpmgt Register Ldocntl Register Bgpd Bit Ldopd Bit Usbldoen BitClkoutsr Output Slew Rate Control Register Osrcr 1C16hEmifsr S05PD S04PD S03PD S02PD S01PD S00PD S15PD S14PD S13PD S12PD S11PD S10PDS15PD S05PDA20PD A19PD A18PD A17PD A16PD A15PD INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuINT1PU PD15PD A20PDDMA Controller Configuration DMA Synchronization Events DMA Configuration Registers52. Channel Synchronization Events for DMA Controllers 53. System Registers Related to the DMA Controllers54. DMA Interrupt Flag Register Dmaifr Field Descriptions 55. DMA Interrupt Enable Register Dmaier Field DescriptionsCH1EVT Peripheral ResetCH0EVT CH3EVTPeripheral Reset Control Register Prcr 1C05h Peripheral Software Reset Counter Register Psrcr 1C04hCount PG4RSTPG3RST Emif and USB Byte Access61. Effect of Usbscr Bytemode Bits on USB Access 60. Effect of Bytemode Bits on Emif AccessesBytemode Setting CPU Access to USB Register Emif System Control Register Escr 1C33h63. Emif Clock Divider Register Ecdr Field Descriptions Emif Clock Divider Register Ecdr 1C26hEdiv DSP Products ApplicationsRfid

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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