Texas Instruments TMS3320C5515 Functional Description, Multiplier and Dividers, Sysclk Frequency

Page 24

System Clock Generator

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Figure 1-4. Clock Generator

CLKSEL

CLKIN

RTC_CLKOUT RTC_XI

32.768

 

 

 

 

 

 

 

 

RTC

 

 

 

 

 

 

 

 

KHz

 

 

 

 

 

 

 

 

OSC

RTC_XO

 

 

 

 

 

1

 

 

LS

0

CLKREF

RTC Clock

 

LS

 

RTC

 

 

 

 

1

 

 

 

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLL

 

Divider

 

Reference

 

 

0

PLLIN

 

PLLOUT

 

 

Divider

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CGCR2[RDBYPASS]

 

 

0

 

LS

1

1

SYSCLK

 

0

CGCR4.

 

[OUTDIVEN]

 

 

CCR2.

 

[SYSCLKSEL]

1.4.2 Functional Description

The following sections describe the multiplier and dividers of the clock generator.

1.4.2.1Multiplier and Dividers

The clock generator has a one multiplier and a two programmable dividers: one before the PLL input and one on the PLL output. The PLL can be programmed to multiply the PLL input clock, PLLIN, using a x4 to x4099 multiplier value. The reference clock divider can be programmed to divide the clock generator input clock from a /4 to /4099 divider ratio and may be bypassed. The Reference Divider and RDBYPASS mux must be programmed such that the PLLIN frequency range is 32.786 KHz to 170 KHz. At the output of the PLL, the output divider can be used to divide the PLL output clock, PLLOUT, from a /1 to a /128 divider ratio and may also be bypassed. The PLL output, PLLOUT, frequency must be programmed within the range of at least 60 MHz and no more than the maximum operating frequency defined by the datasheet, Fsysclk_max parameter. See Table 1-10for allowed values of PLLIN, PLLOUT, and SYSCLK. Keep in mind that programming the output divider with an odd divisor value other than 1 will result in a non-50% duty cycle SYSCLK. This is not a problem for any of the on-chip logic, but the non-50% duty cycle will be visible on chip pins such as EM_SDCLK (in full-rate mode) and CLKOUT. See Table 1-10for allowed values of PLLIN, PLLOUT, and SYSCLK.

The multiplier and divider ratios are controlled through the PLL control registers. The M bits define the multiplier rate. The RDRATIO and ODRATIO bits define the divide ratio of the reference divider and programmable output divider, respectively. The RDBYPASS and OUTDIVEN bits are used to enable or bypass the dividers. Table 1-5lists the formulas for the output frequency based on the setting of these bits.

The clock generator must be placed in BYPASS MODE when any PLL dividers or multipliers are changed. Then, it must remain in BYPASS MODE for at least 4 mS before switching to PLL MODE.

Table 1-5. PLL Output Frequency Configuration

RDBYPASS

OUTDIVEN

 

SYSCLK Frequency

 

 

 

 

 

 

 

 

 

 

 

 

0

0

CLKREF ⋅

 

(M + 4 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RDRATIO + 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

CLKREF ⋅

(M + 4 )

 

 

⋅

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

RDRATIO + 4

ODRATIO + 1

 

 

 

 

 

 

 

 

 

 

 

1

0

 

CLKREF ⋅ M + 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

CLKREF ⋅ M + 4⋅

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ODRATIO + 1

 

 

 

 

 

 

 

 

 

 

 

 

1.4.2.2Powering Down and Powering Up the System PLL

To save power, you can put the PLL in its power down mode. You can power down the PLL by setting the PLL_PWRDN = 1 in the clock generator control register CGCR1. However, before powering down the PLL, you must first place the clock generator in bypass mode.

24

System Control

SPRUFX5A –October 2010 –Revised November 2010

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Block Diagram Functional Block DiagramUsing FFT Accelerator ROM routines CPU CoreFFT Hardware Accelerator AddressPower Management PeripheralsSystem Memory Program/Data Memory MapOn-Chip Dual-Access RAM Daram Daram BlocksCPU Byte Address Range DaramOn-Chip Single-Access RAM Saram Saram BlocksSaram On-Chip Single-Access Read-Only Memory Sarom Sarom BlocksExternal Memory Asynchronous Emif Interface2 I/O Memory Map OverviewDevice Clocking DSP Clocking Diagram Clock Domains PLL Output Frequency Configuration Powering Down and Powering Up the System PLLFunctional Description Multiplier and DividersClkout Pin SRCBit Field Value Description Configuration DSP Reset Conditions of the System Clock GeneratorClock Generator During Reset Clock Generator After ResetRegister Bits Used in the Bypass Mode Setting the System Clock Frequency In the Bypass ModeEntering and Exiting the PLL Mode Register Bits Used in the PLL ModeSetting the Output Frequency for the PLL Mode CV DD = 1.05 CV DD = 1.3 Clock Signal NameFrequency Ranges for Internal Clocks 10. PLL Clock Frequency RangesClock Generator Registers Lock TimeSoftware Steps To Modify Multiplier and Divider Ratios 12. Clock Generator RegistersClock Generator Control Register 1 CGCR1 1C20h Clock Generator Control Register 2 CGCR2 1C21hClock Generator Control Register 3 CGCR3 1C22h Clock Generator Control Register 4 CGCR4 1C23hInit Clock Configuration Register 1 CCR1 1C1Eh 17. Clock Configuration Register 1 CCR1 Field DescriptionsClock Configuration Register 2 CCR2 1C1Fh 18. Clock Configuration Register 2 CCR2 Field DescriptionsPower Domains 19. Power Management Features20. DSP Power Domains Power Domains DescriptionClock Management CPU Domain Clock Gating Daram21. Idle Configuration Register ICR Field Descriptions Hwai Iporti Mporti Xporti Dporti Idlecfg CpuiHwai Valid Idle Configurations 22. Idle Status Register Istr Field Descriptions23. CPU Clock Domain Idle Requirements Clock Configuration Process Peripheral Domain Clock GatingTo Idle the Following Module/Port XportMMCSD0CG DMA0CG Uartcg Spicg I2S3CG SysclkdisMMCSD0CG Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg Lcdcg AnaregcgUrtclkstpack UrtclkstpreqUsbclkstpack UsbclkstpreqClock Generator Domain Clock Gating USB Domain Clock GatingBit Field EmfclkstpackUSB System Control Register Usbscr 1C32h 27. USB System Control Register Usbscr Field DescriptionsUsbpwdn Usbsessend Usbvbusdet Usbpllen UsbpwdnRTC Domain Clock Gating UsbdatpolUsboscbiasdis UsboscdisStatic Power Management RTC Power Management Register Rtcpmgt 1930hRTC Interrupt Flag Register Rtcintfl 1920h 29. RTC Interrupt Flag Register Rtcintfl Field DescriptionsInternal Memory Low Power Modes RAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28hMode CV DD Voltage 30. On-Chip Memory Standby Modes21. RAM Sleep Mode Control Register2 0x1C2A Power Configurations 31. Power ConfigurationsDV DDRTC, Ldoi IDLE3IDLE2 Procedure IDLE3 Procedure Core Voltage Scaling32. Interrupt Table HEX BytesIFR and IER Registers 33. IFR0 and IER0 Bit DescriptionsInterrupt Timing 34. IFR1 and IER1 Bit DescriptionsRtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 RtosTimer Interrupt Aggregation Flag Register Tiafr 1C14h Gpio Interrupt Enable and Aggregation Flag RegistersDMA Interrupt Enable and Aggregation Flag Registers Device Identification 35. Die ID RegistersDie ID Register 0 DIEIDR0 1C40h 36. Die ID Register 0 DIEIDR0 Field DescriptionsDie ID Register 1 DIEIDR1 1C41h 37. Die ID Register 1 DIEIDR1 Field DescriptionsDie ID Register 3 DIEIDR3150 1C43h 39. Die ID Register 3 DIEIDR3150 Field DescriptionsDie ID Register 4 DIEIDR4 1C44h 40. Die ID Register 4 DIEIDR4 Field DescriptionsDie ID Register 6 DIEIDR6 1C46h 42. Die ID Register 6 DIEIDR6 Field DescriptionsDie ID Register 7 DIEIDR7 1C47h 43. Die ID Register 7 DIEIDR7 Field DescriptionsDevice Configuration External Bus Selection Register Ebsr44. Ebsr Register Bit Descriptions Field Descriptions LDO Control Register 7004h LDO ControlA17MODE A16MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions 46. Ldocntl Register Bit Descriptions Field Descriptions 47. LDO Controls MatrixRtcpmgt Register Ldocntl Register Bgpd Bit Ldopd Bit Usbldoen BitOutput Slew Rate Control Register Osrcr 1C16h ClkoutsrEmifsr S15PD S14PD S13PD S12PD S11PD S10PD S05PD S04PD S03PD S02PD S01PD S00PDS15PD S05PDINT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu Tckpu A20PD A19PD A18PD A17PD A16PD A15PDINT1PU A20PD PD15PDDMA Controller Configuration DMA Configuration Registers DMA Synchronization Events52. Channel Synchronization Events for DMA Controllers 53. System Registers Related to the DMA Controllers55. DMA Interrupt Enable Register Dmaier Field Descriptions 54. DMA Interrupt Flag Register Dmaifr Field DescriptionsPeripheral Reset CH1EVTCH0EVT CH3EVTPeripheral Software Reset Counter Register Psrcr 1C04h Peripheral Reset Control Register Prcr 1C05hCount PG4RSTEmif and USB Byte Access PG3RST60. Effect of Bytemode Bits on Emif Accesses 61. Effect of Usbscr Bytemode Bits on USB AccessBytemode Setting CPU Access to USB Register Emif System Control Register Escr 1C33hEmif Clock Divider Register Ecdr 1C26h 63. Emif Clock Divider Register Ecdr Field DescriptionsEdiv Products Applications DSPRfid

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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