Texas Instruments TMS3320C5515 manual Clock Generator Domain Clock Gating, USB Domain Clock Gating

Page 43

www.ti.comPower Management

Table 1-26. Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) Field Descriptions

 

 

 

(continued)

 

 

 

 

Bit

Field

Value

Description

 

 

 

 

1

EMFCLKSTPACK

 

EMIF clock stop acknowledge bit. This bit is set to 1 when the EMIF has acknowledged a

 

 

 

request for its clock to be stopped. The EMIF clock should not be stopped until this bit is

 

 

 

set to 1.

 

 

0

The request to stop the peripheral clock has not been acknowledged.

 

 

1

The request to stop the peripheral clock has been acknowledged, the clock can be

 

 

 

stopped.

 

 

 

 

0

EMFCLKSTPREQ

 

EMIF peripheral clock stop request bit. When disabling the EMIF internal peripheral clock,

 

 

 

you must set this bit to 1 to request permission to stop the clock. After the EMIF

 

 

 

acknowledges the request (EMFCLKSTPACK = 1) you can stop the clock through the

 

 

 

peripheral clock gating control register 1 (PCGCR1). When enabling the EMIF internal

 

 

 

clock, enable the clock through PCGCR1, then set EMFCKLSTPREQ to 0.

 

 

0

Normal operating mode.

 

 

1

Request permission to stop the peripheral clock.

 

 

 

 

1.5.3.2.3 Clock Configuration Process

The clock configuration indicates which portions of the peripheral clock domain will be idle, and which will be active. The basic steps to the clock configuration process are:

1.Wait for completion of all DMA transfers. You can poll the DMA transfer status and disable DMA transfers through the DMA registers.

2.If idling the EMIF, USB, and UART clock, set the corresponding clock stop request bit in CLKSTOP.

3.Wait for confirmation from the module that its clock can be stopped by polling the clock stop acknowledge bits of CLKSTOP.

4.Set the clock configuration for the peripheral domain through PCGCR1 and PCGCR2. The clock configuration takes place as soon as you write to these registers; the idle instruction is not required

1.5.3.3Clock Generator Domain Clock Gating

To save power, the system clock generator can be placed in its BYPASS MODE and its PLL can be placed in power down mode. When the system clock generator is in the BYPASS MODE, the clock generator is not used and the system clock (SYSCLK) is driven by either the CLKIN pin or the real-time clock (RTC). For more information entering and exiting the bypass mode of the clock generator, see Section 1.4.3.1.1.

When the clock generator is placed in its bypass mode, the PLL continues to generate a clock output. You can save additional power by powering down the PLL. Section 1.4.2.2 provides more information on powering down the PLL.

1.5.3.4USB Domain Clock Gating

The USB peripheral has two clock domains. The first is a high speed domain that has its clock supplied by a dedicated USB PLL. The reference clock for the USB PLL is the 12.0 MHz USB oscillator. The clock output from the PLL must support the serial data stream that, in high-speed mode, is at a rate of 480 Mb/s. The second clock into the USB peripheral handles the data once it has been packetized and transported in parallel fashion. This clock supports all of the USB registers, CDMA, FIFO, etc., and is clocked by SYSCLK. In order to keep up with the serial data stream, the USB requires SYSCLK to be at least 30 MHz for low-speed/full-speed modes and at least 60 MHz for high-speed mode.

By stopping both of these clocks, it is possible to reduce the USB'sactive power consumption (in the digital logic) to zero.

NOTE: Stopping clocks to a peripheral only affects active power consumption; it does not affect leakage power consumption. USB leakage power consumption can be reduced to zero by not powering the USB.

SPRUFX5A –October 2010 –Revised November 2010

System Control

43

Submit Documentation Feedback

 

 

Copyright © 2010, Texas Instruments Incorporated

Page 42 Page 44
Image 43
Page 42 Page 44
Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Functional Block Diagram Block DiagramAddress Using FFT Accelerator ROM routinesCPU Core FFT Hardware AcceleratorPeripherals Power ManagementProgram/Data Memory Map System MemoryDaram On-Chip Dual-Access RAM DaramDaram Blocks CPU Byte Address RangeSaram Blocks On-Chip Single-Access RAM SaramSaram Asynchronous Emif Interface On-Chip Single-Access Read-Only Memory SaromSarom Blocks External MemoryOverview 2 I/O Memory MapDevice Clocking DSP Clocking Diagram Clock Domains Multiplier and Dividers PLL Output Frequency ConfigurationPowering Down and Powering Up the System PLL Functional DescriptionSRC Clkout PinBit Field Value Description Clock Generator After Reset ConfigurationDSP Reset Conditions of the System Clock Generator Clock Generator During ResetRegister Bits Used in the PLL Mode Register Bits Used in the Bypass ModeSetting the System Clock Frequency In the Bypass Mode Entering and Exiting the PLL Mode10. PLL Clock Frequency Ranges Setting the Output Frequency for the PLL ModeCV DD = 1.05 CV DD = 1.3 Clock Signal Name Frequency Ranges for Internal Clocks12. Clock Generator Registers Clock Generator RegistersLock Time Software Steps To Modify Multiplier and Divider RatiosClock Generator Control Register 2 CGCR2 1C21h Clock Generator Control Register 1 CGCR1 1C20hClock Generator Control Register 4 CGCR4 1C23h Clock Generator Control Register 3 CGCR3 1C22hInit 18. Clock Configuration Register 2 CCR2 Field Descriptions Clock Configuration Register 1 CCR1 1C1Eh17. Clock Configuration Register 1 CCR1 Field Descriptions Clock Configuration Register 2 CCR2 1C1Fh19. Power Management Features Power DomainsPower Domains Description 20. DSP Power DomainsClock Management Daram CPU Domain Clock GatingHwai Iporti Mporti Xporti Dporti Idlecfg Cpui 21. Idle Configuration Register ICR Field DescriptionsHwai 22. Idle Status Register Istr Field Descriptions Valid Idle Configurations23. CPU Clock Domain Idle Requirements Xport Clock Configuration ProcessPeripheral Domain Clock Gating To Idle the Following Module/PortSysclkdis MMCSD0CG DMA0CG Uartcg Spicg I2S3CGMMCSD0CG Anaregcg Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg LcdcgUsbclkstpreq UrtclkstpackUrtclkstpreq UsbclkstpackEmfclkstpack Clock Generator Domain Clock GatingUSB Domain Clock Gating Bit FieldUsbpwdn USB System Control Register Usbscr 1C32h27. USB System Control Register Usbscr Field Descriptions Usbpwdn Usbsessend Usbvbusdet UsbpllenUsboscdis RTC Domain Clock GatingUsbdatpol UsboscbiasdisRTC Power Management Register Rtcpmgt 1930h Static Power Management29. RTC Interrupt Flag Register Rtcintfl Field Descriptions RTC Interrupt Flag Register Rtcintfl 1920h30. On-Chip Memory Standby Modes Internal Memory Low Power ModesRAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28h Mode CV DD Voltage21. RAM Sleep Mode Control Register2 0x1C2A IDLE3 Power Configurations31. Power Configurations DV DDRTC, LdoiIDLE2 Procedure Core Voltage Scaling IDLE3 ProcedureHEX Bytes 32. Interrupt Table33. IFR0 and IER0 Bit Descriptions IFR and IER RegistersRtos Interrupt Timing34. IFR1 and IER1 Bit Descriptions Rtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3Gpio Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hDMA Interrupt Enable and Aggregation Flag Registers 35. Die ID Registers Device Identification37. Die ID Register 1 DIEIDR1 Field Descriptions Die ID Register 0 DIEIDR0 1C40h36. Die ID Register 0 DIEIDR0 Field Descriptions Die ID Register 1 DIEIDR1 1C41h40. Die ID Register 4 DIEIDR4 Field Descriptions Die ID Register 3 DIEIDR3150 1C43h39. Die ID Register 3 DIEIDR3150 Field Descriptions Die ID Register 4 DIEIDR4 1C44h43. Die ID Register 7 DIEIDR7 Field Descriptions Die ID Register 6 DIEIDR6 1C46h42. Die ID Register 6 DIEIDR6 Field Descriptions Die ID Register 7 DIEIDR7 1C47hExternal Bus Selection Register Ebsr Device Configuration44. Ebsr Register Bit Descriptions Field Descriptions A16MODE LDO Control Register 7004hLDO Control A17MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions Bgpd Bit Ldopd Bit Usbldoen Bit 46. Ldocntl Register Bit Descriptions Field Descriptions47. LDO Controls Matrix Rtcpmgt Register Ldocntl RegisterClkoutsr Output Slew Rate Control Register Osrcr 1C16hEmifsr S05PD S15PD S14PD S13PD S12PD S11PD S10PDS05PD S04PD S03PD S02PD S01PD S00PD S15PDA20PD A19PD A18PD A17PD A16PD A15PD INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuINT1PU PD15PD A20PDDMA Controller Configuration 53. System Registers Related to the DMA Controllers DMA Configuration RegistersDMA Synchronization Events 52. Channel Synchronization Events for DMA Controllers54. DMA Interrupt Flag Register Dmaifr Field Descriptions 55. DMA Interrupt Enable Register Dmaier Field DescriptionsCH3EVT Peripheral ResetCH1EVT CH0EVTPG4RST Peripheral Software Reset Counter Register Psrcr 1C04hPeripheral Reset Control Register Prcr 1C05h CountPG3RST Emif and USB Byte AccessEmif System Control Register Escr 1C33h 60. Effect of Bytemode Bits on Emif Accesses61. Effect of Usbscr Bytemode Bits on USB Access Bytemode Setting CPU Access to USB Register63. Emif Clock Divider Register Ecdr Field Descriptions Emif Clock Divider Register Ecdr 1C26hEdiv DSP Products ApplicationsRfid

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

One of the main features of the TMS3320C5515 is its 32-bit architecture, which allows for a high level of precision in digital signal computation. The processor is capable of executing complex mathematical algorithms, making it suitable for tasks that require high-speed data processing, such as speech recognition and audio filtering. With a native instruction set optimized for DSP applications, the TMS3320C5515 can perform multiply-accumulate operations in a single cycle, significantly enhancing computational efficiency.

The TMS3320C5515 employs advanced technologies including a Harvard architecture that separates instruction and data memory, enabling simultaneous access and improving performance. Its dual data buses enhance throughput by allowing multi-channel processing, making it particularly effective for real-time applications where timely data manipulation is critical. The device supports a wide range of peripherals, facilitating connections to various sensors and communication systems, which is vital in embedded applications.

In terms of characteristics, the TMS3320C5515 operates at an impressive clock speed, providing the computational power necessary to handle demanding tasks. The device is optimized for low power consumption, making it ideal for battery-operated applications without sacrificing performance. Its flexibility in processing algorithms also allows it to be readily adapted for specific requirements, from audio codecs to modems.

Another noteworthy aspect is the extensive development ecosystem surrounding the TMS3320C5515, which includes software tools, libraries, and support resources designed to accelerate the development process. This allows engineers and developers to bring their projects to market more quickly while minimizing risk.

Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
Top Page Image Contents