Texas Instruments TMS3320C5515 manual Idle Configuration Register ICR Field Descriptions, Hwai

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Power Management

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1.5.3.1.1 Idle Configuration Register (ICR) [0001h] and IDLE Status Register (ISTR) [0002h]

Table 1-21describes the read/write bits of ICR, and Table 1-22describes the read-only bits of ISTR.

NOTE: To prevent an emulation lock up, idle requests to these domains may be overridden or ignored when an emulator is connected to the JTAG port of the DSP.

Figure 1-12. Idle Configuration Register (ICR) [0001h]

15

 

 

 

 

10

9

8

 

 

Reserved

 

 

HWAI

IPORTI

 

 

R/W-0

 

 

R/W-0

R/W-0

7

6

5

 

4

 

1

0

 

 

 

 

 

 

 

 

MPORTI

XPORTI

DPORTI

 

IDLECFG

 

 

CPUI

R/W-0

R/W-0

R/W-0

R/W-0

 

 

R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

Table 1-21. Idle Configuration Register (ICR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

15-10

Reserved

0

Reserved.

 

 

 

 

9

HWAI

 

FFT hardware accelerator idle control bit.

 

 

0

Hardware accelerator remains active after execution of an IDLE instruction.

 

 

1

Hardware accelerator is disabled after execution of an IDLE instruction.

 

 

 

 

8

IPORTI

 

Instruction port idle control bit. The IPORT is used for all external memory instruction accesses.

 

 

0

IPORT remains active after execution of an IDLE instruction.

 

 

1

IPORT is disabled after execution of an IDLE instruction.

 

 

 

 

7

MPORTI

 

Memory port idle control bit. The memory port is used for all DMA, LCD DMA, and USB CDMA

 

 

 

transactions into on-chip memory.

 

 

0

MPORT remains active after execution of an IDLE instruction.

 

 

1

MPORT is disabled after execution of an IDLE instruction.

 

 

 

 

6

XPORTI

 

I/O port idle control bit. The XPORT is used for all CPU I/O memory transactions.

 

 

0

XPORT remains active after execution of an IDLE instruction.

 

 

1

XPORT is disabled after execution of an IDLE instruction.

 

 

 

 

5

DPORTI

 

Data port idle control bit. The data port is used for all CPU external memory data accesses.

 

 

0

DPORT remains active after execution of an IDLE instruction.

 

 

1

DPORT is disabled after execution of an IDLE instruction.

 

 

 

 

4-1

IDLECFG

0111b

Idle configuration bits. You must always set bit 1, 2 and 3 to 1 and bit 4 to 0 before executing the

 

 

 

idle instruction.

 

 

 

 

0

CPUI

 

CPU idle control bit.

 

 

0

CPU remains active after execution of an IDLE instruction.

 

 

1

CPU is disabled after execution of an IDLE instruction.

 

 

 

 

36

System Control

SPRUFX5A –October 2010 –Revised November 2010

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Block Diagram Functional Block DiagramUsing FFT Accelerator ROM routines CPU CoreFFT Hardware Accelerator AddressPower Management PeripheralsSystem Memory Program/Data Memory MapOn-Chip Dual-Access RAM Daram Daram BlocksCPU Byte Address Range DaramOn-Chip Single-Access RAM Saram Saram BlocksSaram On-Chip Single-Access Read-Only Memory Sarom Sarom BlocksExternal Memory Asynchronous Emif Interface2 I/O Memory Map OverviewDevice Clocking DSP Clocking Diagram Clock Domains PLL Output Frequency Configuration Powering Down and Powering Up the System PLLFunctional Description Multiplier and DividersClkout Pin SRCBit Field Value Description Configuration DSP Reset Conditions of the System Clock GeneratorClock Generator During Reset Clock Generator After ResetRegister Bits Used in the Bypass Mode Setting the System Clock Frequency In the Bypass ModeEntering and Exiting the PLL Mode Register Bits Used in the PLL ModeSetting the Output Frequency for the PLL Mode CV DD = 1.05 CV DD = 1.3 Clock Signal NameFrequency Ranges for Internal Clocks 10. PLL Clock Frequency RangesClock Generator Registers Lock TimeSoftware Steps To Modify Multiplier and Divider Ratios 12. Clock Generator RegistersClock Generator Control Register 1 CGCR1 1C20h Clock Generator Control Register 2 CGCR2 1C21hClock Generator Control Register 3 CGCR3 1C22h Clock Generator Control Register 4 CGCR4 1C23hInit Clock Configuration Register 1 CCR1 1C1Eh 17. Clock Configuration Register 1 CCR1 Field DescriptionsClock Configuration Register 2 CCR2 1C1Fh 18. Clock Configuration Register 2 CCR2 Field DescriptionsPower Domains 19. Power Management Features20. DSP Power Domains Power Domains DescriptionClock Management CPU Domain Clock Gating Daram21. Idle Configuration Register ICR Field Descriptions Hwai Iporti Mporti Xporti Dporti Idlecfg CpuiHwai Valid Idle Configurations 22. Idle Status Register Istr Field Descriptions23. CPU Clock Domain Idle Requirements Clock Configuration Process Peripheral Domain Clock GatingTo Idle the Following Module/Port XportMMCSD0CG DMA0CG Uartcg Spicg I2S3CG SysclkdisMMCSD0CG Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg Lcdcg AnaregcgUrtclkstpack UrtclkstpreqUsbclkstpack UsbclkstpreqClock Generator Domain Clock Gating USB Domain Clock GatingBit Field EmfclkstpackUSB System Control Register Usbscr 1C32h 27. USB System Control Register Usbscr Field DescriptionsUsbpwdn Usbsessend Usbvbusdet Usbpllen UsbpwdnRTC Domain Clock Gating UsbdatpolUsboscbiasdis UsboscdisStatic Power Management RTC Power Management Register Rtcpmgt 1930hRTC Interrupt Flag Register Rtcintfl 1920h 29. RTC Interrupt Flag Register Rtcintfl Field DescriptionsInternal Memory Low Power Modes RAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28hMode CV DD Voltage 30. On-Chip Memory Standby Modes21. RAM Sleep Mode Control Register2 0x1C2A Power Configurations 31. Power ConfigurationsDV DDRTC, Ldoi IDLE3IDLE2 Procedure IDLE3 Procedure Core Voltage Scaling32. Interrupt Table HEX BytesIFR and IER Registers 33. IFR0 and IER0 Bit DescriptionsInterrupt Timing 34. IFR1 and IER1 Bit DescriptionsRtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 RtosTimer Interrupt Aggregation Flag Register Tiafr 1C14h Gpio Interrupt Enable and Aggregation Flag RegistersDMA Interrupt Enable and Aggregation Flag Registers Device Identification 35. Die ID RegistersDie ID Register 0 DIEIDR0 1C40h 36. Die ID Register 0 DIEIDR0 Field DescriptionsDie ID Register 1 DIEIDR1 1C41h 37. Die ID Register 1 DIEIDR1 Field DescriptionsDie ID Register 3 DIEIDR3150 1C43h 39. Die ID Register 3 DIEIDR3150 Field DescriptionsDie ID Register 4 DIEIDR4 1C44h 40. Die ID Register 4 DIEIDR4 Field DescriptionsDie ID Register 6 DIEIDR6 1C46h 42. Die ID Register 6 DIEIDR6 Field DescriptionsDie ID Register 7 DIEIDR7 1C47h 43. Die ID Register 7 DIEIDR7 Field DescriptionsDevice Configuration External Bus Selection Register Ebsr44. Ebsr Register Bit Descriptions Field Descriptions LDO Control Register 7004h LDO ControlA17MODE A16MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions 46. Ldocntl Register Bit Descriptions Field Descriptions 47. LDO Controls MatrixRtcpmgt Register Ldocntl Register Bgpd Bit Ldopd Bit Usbldoen BitOutput Slew Rate Control Register Osrcr 1C16h ClkoutsrEmifsr S15PD S14PD S13PD S12PD S11PD S10PD S05PD S04PD S03PD S02PD S01PD S00PDS15PD S05PDINT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu Tckpu A20PD A19PD A18PD A17PD A16PD A15PDINT1PU A20PD PD15PDDMA Controller Configuration DMA Configuration Registers DMA Synchronization Events52. Channel Synchronization Events for DMA Controllers 53. System Registers Related to the DMA Controllers55. DMA Interrupt Enable Register Dmaier Field Descriptions 54. DMA Interrupt Flag Register Dmaifr Field DescriptionsPeripheral Reset CH1EVTCH0EVT CH3EVTPeripheral Software Reset Counter Register Psrcr 1C04h Peripheral Reset Control Register Prcr 1C05hCount PG4RSTEmif and USB Byte Access PG3RST60. Effect of Bytemode Bits on Emif Accesses 61. Effect of Usbscr Bytemode Bits on USB AccessBytemode Setting CPU Access to USB Register Emif System Control Register Escr 1C33hEmif Clock Divider Register Ecdr 1C26h 63. Emif Clock Divider Register Ecdr Field DescriptionsEdiv Products Applications DSPRfid

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

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