Texas Instruments TMS3320C5515 manual USB System Control Register Usbscr 1C32h, Usbpwdn

Page 44

Power Management

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1.5.3.4.1 Clock Configuration Process

The clock configuration process for the USB clock domain consists of disabling the USB peripheral clock followed by disabling the USB on-chip oscillator. This procedure will completely shut off USB module, which does not comply with USB suspend/resume protocol.

To set the clock configuration of the USB clock domain to idle follow these steps:

1.Set the SUSPENDM bit in FADDR register. For more information about the SUSPENDM bit, see the TMS320C5515/14/05/04 DSP Universal Serial Bus 2.0 (USB) Controller User's Guide (SPRUGH9).

2.Set the USB clock stop request bit (USBCLKSTREQ) in the CLKSTOP register to request permission to shut off the USB peripheral clock.

3.Wait until the USB acknowledges the clock stop request by polling the USB clock stop acknowledge bit (USBCLKSTPACK) in the CLKSTOP register.

4.Disable the USB peripheral clock by setting USBCG = 1 in the peripheral clock gating control register 2 (PCGCR2).

5.Disable the USB oscillator by setting USBOSCDIS = 1 in the USB system control register (USBSCR).

To enable the USB clock domain, follow these steps:

1.Enable the USB oscillator by setting USBOSCDIS = 0 in USBSCR.

2.Wait for the oscillator to stabilize. Refer to the device-specific data manual for oscillator stabilization time.

3.Enable the USB peripheral clock by setting USBCG = 0 in the peripheral clock gating control register 2 (PCGCR2).

4.Clear the USB clock stop request bit (USBCLKSTREQ) in the CLKSTOP register.

5.Clear the SUSPENDM bit in FADDR register.

1.5.3.4.2 USB System Control Register (USBSCR) [1C32h]

The USB system control register is used to disable the USB on-chip oscillator and to power-down the USB.

The USB system control register (USBSCR) is shown in Figure 1-17and described in Table 1-27.

Figure 1-17. USB System Control Register (USBSCR) [1C32h]

15

14

13

 

12

11

 

 

 

8

USBPWDN

USBSESSEND

USBVBUSDET

 

USBPLLEN

 

Reserved

 

 

R/W-1

R/W-0

R/W-1

R/W-0

 

R-0

 

 

7

6

5

 

4

3

2

 

1

0

 

 

 

 

 

 

 

 

Reserved

USBDATPOL

Reserved

USBOSCBIASDIS

USBOSCDIS

 

 

BYTEMODE

 

 

 

 

 

 

 

 

 

 

R-0

R/W-1

R-0

 

R/W-1

R/W-1

 

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 1-27. USB System Control Register (USBSCR) Field Descriptions

Bit

Field

Value

Description

 

 

 

 

15

USBPWDN

 

USB module power. Asserting USBPWDN puts the USB PHY and PLL in their lowest

 

 

 

power state. The USB peripheral is not operational in this state.

 

 

0

USB module is powered.

 

 

1

USB module is powered-down.

 

 

 

 

14

USBSESSEND

 

USB VBUS session end comparator enable. The USB VBUS pin has two comparators

 

 

 

that monitor the voltage level on the pin. These comparators can be disabled for power

 

 

 

savings when not needed.

 

 

0

USB VBUS session end comparator is disabled.

 

 

1

USB VBUS session end comparator is enabled.

 

 

 

 

44

System Control

SPRUFX5A –October 2010 –Revised November 2010

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Submit Documentation Feedback List of Tables Submit Documentation Feedback Submit Documentation Feedback Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Submit Documentation Feedback Block Diagram Functional Block DiagramUsing FFT Accelerator ROM routines CPU CoreFFT Hardware Accelerator AddressPower Management PeripheralsSystem Memory Program/Data Memory MapOn-Chip Dual-Access RAM Daram Daram BlocksCPU Byte Address Range DaramSaram On-Chip Single-Access RAM SaramSaram Blocks On-Chip Single-Access Read-Only Memory Sarom Sarom BlocksExternal Memory Asynchronous Emif Interface2 I/O Memory Map OverviewDevice Clocking DSP Clocking Diagram Clock Domains PLL Output Frequency Configuration Powering Down and Powering Up the System PLLFunctional Description Multiplier and DividersBit Field Value Description Clkout PinSRC Configuration DSP Reset Conditions of the System Clock GeneratorClock Generator During Reset Clock Generator After ResetRegister Bits Used in the Bypass Mode Setting the System Clock Frequency In the Bypass ModeEntering and Exiting the PLL Mode Register Bits Used in the PLL ModeSetting the Output Frequency for the PLL Mode CV DD = 1.05 CV DD = 1.3 Clock Signal NameFrequency Ranges for Internal Clocks 10. PLL Clock Frequency RangesClock Generator Registers Lock TimeSoftware Steps To Modify Multiplier and Divider Ratios 12. Clock Generator RegistersClock Generator Control Register 1 CGCR1 1C20h Clock Generator Control Register 2 CGCR2 1C21hInit Clock Generator Control Register 3 CGCR3 1C22hClock Generator Control Register 4 CGCR4 1C23h Clock Configuration Register 1 CCR1 1C1Eh 17. Clock Configuration Register 1 CCR1 Field DescriptionsClock Configuration Register 2 CCR2 1C1Fh 18. Clock Configuration Register 2 CCR2 Field DescriptionsPower Domains 19. Power Management FeaturesClock Management 20. DSP Power DomainsPower Domains Description CPU Domain Clock Gating DaramHwai 21. Idle Configuration Register ICR Field DescriptionsHwai Iporti Mporti Xporti Dporti Idlecfg Cpui 23. CPU Clock Domain Idle Requirements Valid Idle Configurations22. Idle Status Register Istr Field Descriptions Clock Configuration Process Peripheral Domain Clock GatingTo Idle the Following Module/Port XportMMCSD0CG DMA0CG Uartcg Spicg I2S3CG SysclkdisMMCSD0CG Anaregcg DMA3CG DMA2CG DMA1CG Usbcg Sarcg Lcdcg AnaregcgUrtclkstpack UrtclkstpreqUsbclkstpack UsbclkstpreqClock Generator Domain Clock Gating USB Domain Clock GatingBit Field EmfclkstpackUSB System Control Register Usbscr 1C32h 27. USB System Control Register Usbscr Field DescriptionsUsbpwdn Usbsessend Usbvbusdet Usbpllen UsbpwdnRTC Domain Clock Gating UsbdatpolUsboscbiasdis UsboscdisStatic Power Management RTC Power Management Register Rtcpmgt 1930hRTC Interrupt Flag Register Rtcintfl 1920h 29. RTC Interrupt Flag Register Rtcintfl Field DescriptionsInternal Memory Low Power Modes RAM Sleep Mode Control Register 1 RAMSLPMDCNTLR1 1C28hMode CV DD Voltage 30. On-Chip Memory Standby Modes21. RAM Sleep Mode Control Register2 0x1C2A Power Configurations 31. Power ConfigurationsDV DDRTC, Ldoi IDLE3IDLE2 Procedure IDLE3 Procedure Core Voltage Scaling32. Interrupt Table HEX BytesIFR and IER Registers 33. IFR0 and IER0 Bit DescriptionsInterrupt Timing 34. IFR1 and IER1 Bit DescriptionsRtos Dlog Berr I2C Emif Gpio USB SPI RTC RCV3 XMT3 RtosDMA Interrupt Enable and Aggregation Flag Registers Timer Interrupt Aggregation Flag Register Tiafr 1C14hGpio Interrupt Enable and Aggregation Flag Registers Device Identification 35. Die ID RegistersDie ID Register 0 DIEIDR0 1C40h 36. Die ID Register 0 DIEIDR0 Field DescriptionsDie ID Register 1 DIEIDR1 1C41h 37. Die ID Register 1 DIEIDR1 Field DescriptionsDie ID Register 3 DIEIDR3150 1C43h 39. Die ID Register 3 DIEIDR3150 Field DescriptionsDie ID Register 4 DIEIDR4 1C44h 40. Die ID Register 4 DIEIDR4 Field DescriptionsDie ID Register 6 DIEIDR6 1C46h 42. Die ID Register 6 DIEIDR6 Field DescriptionsDie ID Register 7 DIEIDR7 1C47h 43. Die ID Register 7 DIEIDR7 Field DescriptionsDevice Configuration External Bus Selection Register Ebsr44. Ebsr Register Bit Descriptions Field Descriptions LDO Control Register 7004h LDO ControlA17MODE A16MODE45. Rtcpmgt Register Bit Descriptions Field Descriptions 46. Ldocntl Register Bit Descriptions Field Descriptions 47. LDO Controls MatrixRtcpmgt Register Ldocntl Register Bgpd Bit Ldopd Bit Usbldoen BitEmifsr Output Slew Rate Control Register Osrcr 1C16hClkoutsr S15PD S14PD S13PD S12PD S11PD S10PD S05PD S04PD S03PD S02PD S01PD S00PDS15PD S05PDINT1PU INT1PU INT0PU Resetpu EMU01PU Tdipu Tmspu TckpuA20PD A19PD A18PD A17PD A16PD A15PD A20PD PD15PDDMA Controller Configuration DMA Configuration Registers DMA Synchronization Events52. Channel Synchronization Events for DMA Controllers 53. System Registers Related to the DMA Controllers55. DMA Interrupt Enable Register Dmaier Field Descriptions 54. DMA Interrupt Flag Register Dmaifr Field DescriptionsPeripheral Reset CH1EVTCH0EVT CH3EVTPeripheral Software Reset Counter Register Psrcr 1C04h Peripheral Reset Control Register Prcr 1C05hCount PG4RSTEmif and USB Byte Access PG3RST60. Effect of Bytemode Bits on Emif Accesses 61. Effect of Usbscr Bytemode Bits on USB AccessBytemode Setting CPU Access to USB Register Emif System Control Register Escr 1C33hEdiv Emif Clock Divider Register Ecdr 1C26h63. Emif Clock Divider Register Ecdr Field Descriptions Rfid Products ApplicationsDSP

TMS3320C5515 specifications

The Texas Instruments TMS3320C5515 is a highly specialized digital signal processor (DSP) designed for a wide range of applications, including telecommunications, audio processing, and other signal-intensive tasks. As part of the TMS320 family of DSPs, the TMS3320C5515 leverages TI's extensive experience in signal processing technology, delivering robust performance and reliability.

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Overall, the Texas Instruments TMS3320C5515 stands out as a powerful DSP solution, equipped with features that cater to the needs of various industries. Its combination of performance, efficiency, and versatile application makes it an attractive choice for engineers working in signal processing.
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