Analog Devices AD9912 specifications Features, Applications, General Description

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1 GSPS Direct Digital Synthesizer with 14-Bit DAC

AD9912

FEATURES

1 GSPS internal clock speed (up to 400 MHz output directly) Integrated 1 GSPS 14-bit DAC

48-bit frequency tuning word with 4 µHz resolution Differential HSTL comparator

Flexible system clock input accepts either crystal or external reference clock

On-chip low noise PLL REFCLK multiplier 2 SpurKiller channels

Low jitter clock doubler for frequencies up to 750 MHz Single-ended CMOS comparator; frequencies of <150 MHz Programmable output divider for CMOS output

Serial I/O control

Excellent dynamic performance Software controlled power-down Available in two 64-lead LFCSP packages Residual phase noise @ 250 MHz

10 Hz offset: −113 dBc/Hz

1 kHz offset: −133 dBc/Hz

100 kHz offset: −153 dBc/Hz

40 MHz offset: −161 dBc/Hz

APPLICATIONS

Agile LO frequency synthesis

Low jitter, fine tune clock generation

Test and measurement equipment

Wireless base stations and controllers

Secure communications

Fast frequency hopping

GENERAL DESCRIPTION

The AD9912 is a direct digital synthesizer (DDS) that features an integrated 14-bit digital-to-analog converter (DAC). The AD9912 features a 48-bit frequency tuning word (FTW) that can synthesize frequencies in step sizes no larger than 4 μHz. Absolute frequency accuracy can be achieved by adjusting the DAC system clock.

The AD9912 also features an integrated system clock phase- locked loop (PLL) that allows for system clock inputs as low as 25 MHz.

The AD9912 operates over an industrial temperature range, spanning −40°C to +85°C.

BASIC BLOCK DIAGRAM

 

AD9912

 

 

 

 

 

 

DAC_OUT

 

S1 TO S4

STARTUP

 

 

 

CONFIGURATION

 

 

 

 

LOGIC

DIRECT

FDBK_IN

FILTER

 

 

 

 

 

 

 

DIGITAL

 

 

 

 

SYNTHESIS

 

 

 

 

CORE

 

OUT

DIGITAL

SERIAL PORT,

 

CLOCK

 

OUTPUT

 

INTERFACE

I/O LOGIC

 

 

 

DRIVERS

OUT_CMOS

 

 

 

 

 

SYSTEM CLOCK

 

 

 

 

MULTIPLIER

 

 

 

 

 

 

06763-001

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Rev. D

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Contents Basic Block Diagram FeaturesApplications General DescriptionTable of Contents DC Specifications SpecificationsParameter Min Typ Max Unit Test Conditions/Comments System Clock Input Total Power DissipationClock Output Drivers Parameter Min Typ Max Unit Test Conditions/Comments AC SpecificationsAvss − Thermal Resistance Absolute Maximum RatingsESD Caution Parameter RatingInput Pin No Output Pin Type Mnemonic Description PIN Configuration and Function DescriptionsIoupdate ResetGND Avss OutbVideo BW Typical Performance CharacteristicsAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Overview Theory of OperationDirect Digital Synthesizer DDS Reconstruction Filter DIGITAL-TO-ANALOG DAC OutputSolving this equation for FTW yields 1024 DAC Spectrum vs. Reconstruction Filter Response Fdbkin InputsFunctional Description Sysclk InputsSysclk PLL Doubler Sysclk PLL multiplier has a 1 GHz VCO at its core Sysclk PLL MultiplierDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLLHarmonic Spur Reduction Output Clock Drivers and 2× Frequency MultiplierSpur Reduction Circuit Diagram Thermal Parameters Thermal PerformancePOWER-ON Reset POWER-UPDefault Output Frequency on POWER-UP Supplies Power Supply PartitioningSerial Control Port PIN Descriptions Serial Control PortOperation of Serial Control Port Instruction Word 16 Bits MSB/LSB First TransfersRead Operations are changed to LSB first orderI15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB FirstParameter Description PLL Register MAPHSR-A Register 0x0010-Power-Down and Enable Register 0x0000-Serial Port ConfigurationPower-up default is defined by the start-up pins Register DescriptionsRegister 0x0013-Reset Not Autoclearing Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-DividerRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x0201-CMOS Driver Register 0x0200-HSTL DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-ReservedRegister 0x0504-Spur a Register 0x0503-Spur aRegister 0x0505-Spur B Register 0x0506-Spur BOutline Dimensions Ordering Guide Model Temperature Range Package Description Package OptionAD9912BCPZ1 AD9912BCPZ-REEL71Rev. D Page 40
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