Analog Devices AD9912 Register Descriptions, Register 0x0000-Serial Port Configuration

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AD9912

I/O REGISTER DESCRIPTIONS

SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005)

Register 0x0000—Serial Port Configuration

Table 13.

Bits	Bit Name	Description
[7:4]		These bits are the mirror image of Bits[3:0].
3	Long instruction	Read-only; the AD9912 supports only long instructions.
2	Soft reset	Resets register map, except for Register 0x0000. Setting this bit forces a soft reset, meaning that S1 to
		S4 are not tristated, nor is their state read when this bit is cleared. The AD9912 assumes the values of
		S1 to S4 that were present during the last hard reset. This bit is not self-clearing, and all other registers
		are restored to their default values after a soft reset.
1	LSB first	Sets bit order for serial port.
		1	= LSB first.
		0	= MSB first. I/O update must occur for the MSB first to take effect.
0	SDO active	Enables SDO pin.
		1	= SDO pin enabled (4-wire serial port mode).
		0	= 3-wire mode.

Register 0x0001—Reserved

Register 0x0002 and Register 0x0003—Part ID (Read-Only)

Register 0x0004—Serial Options

Table 14.

Bits	Bit Name	Description

0	Read buffer register	For buffered registers, serial port readback reads from actual (active) registers instead of the buffer.
		1	= reads the buffered values that take effect during the next I/O update.
		0	= reads values that are currently in effect.

Register 0x0005—Serial Options (Self Clearing)

Table 15.

Bits	Bit Name	Description

0	Register update	Software access to the register update pin function. Writing a 1 to this bit is identical to performing
		an I/O update.

POWER-DOWN AND RESET (REGISTER 0x0010 TO REGISTER 0x0013)

Register 0x0010—Power-Down and Enable

Power-up default is defined by the start-up pins.

Table 16.

Bits	Bit Name	Description

7	PD HSTL driver	Powers down HSTL output driver.
		1 = HSTL driver powered down.
6	Enable CMOS driver	Powers up CMOS output driver.
		1 = CMOS driver on.
5	Enable output doubler	Powers up output clock generator doubler. Output doubler must still be enabled in Register 0x0200.
4	PD SYSCLK PLL	System clock multiplier power-down.
		1 = system clock multiplier powered down.
		If the S4 pin is tied high at power-up or reset, this bit is set, and the default value for Register 0x0010
		is D0, not C0.
1	Full PD	Setting this bit is identical to activating the PD pin and puts all blocks (except serial port) into power-
		down mode. SYSCLK is turned off.
0	Digital PD	Removes clock from most of digital section; leave serial port usable. In contrast to full PD, setting this
		bit does not debias inputs, allowing for quick wake-up.

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Contents Features Basic Block DiagramApplications General DescriptionTable of Contents Parameter Min Typ Max Unit Test Conditions/Comments SpecificationsDC Specifications Clock Output Drivers Total Power DissipationSystem Clock Input AC Specifications Parameter Min Typ Max Unit Test Conditions/CommentsAvss − Absolute Maximum Ratings Thermal ResistanceESD Caution Parameter RatingPIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic DescriptionReset IoupdateGND Avss OutbTypical Performance Characteristics Video BWAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Direct Digital Synthesizer DDS Theory of OperationOverview DIGITAL-TO-ANALOG DAC Output Reconstruction FilterSolving this equation for FTW yields 1024 Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter ResponseSysclk PLL Doubler Sysclk InputsFunctional Description Sysclk PLL Multiplier Sysclk PLL multiplier has a 1 GHz VCO at its coreDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLLOutput Clock Drivers and 2× Frequency Multiplier Harmonic Spur ReductionSpur Reduction Circuit Diagram Thermal Performance Thermal ParametersDefault Output Frequency on POWER-UP POWER-UPPOWER-ON Reset Power Supply Partitioning SuppliesOperation of Serial Control Port Serial Control PortSerial Control Port PIN Descriptions MSB/LSB First Transfers Instruction Word 16 BitsRead Operations are changed to LSB first orderSerial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10Parameter Description Register MAP PLLHSR-A Register 0x0000-Serial Port Configuration Register 0x0010-Power-Down and EnablePower-up default is defined by the start-up pins Register DescriptionsRegister 0x0011-Reserved Register 0x0012-Reset Autoclearing Register 0x0013-Reset Not AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x01A7-FTW0 Frequency Tuning Word Register 0x01A8-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-DividerRegister 0x01A9-FTW0 Frequency Tuning Word Register 0x01AA-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x0200-HSTL Driver Register 0x0201-CMOS DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-ReservedRegister 0x0503-Spur a Register 0x0504-Spur aRegister 0x0505-Spur B Register 0x0506-Spur BOutline Dimensions Model Temperature Range Package Description Package Option Ordering GuideAD9912BCPZ1 AD9912BCPZ-REEL71Rev. D Page 40