Analog Devices AD9912 specifications Table of Contents

Page 2

AD9912

TABLE OF CONTENTS

 

 

Features

1

Applications

1

General Description

1

Basic Block Diagram

1

Revision History

2

Specifications

3

DC Specifications

3

AC Specifications

5

Absolute Maximum Ratings

7

Thermal Resistance

7

ESD Caution

7

Pin Configuration and Function Descriptions

8

Typical Performance Characteristics

10

Input/Output Termination Recommendations

15

Theory of Operation

16

Overview

16

Direct Digital Synthesizer (DDS)

16

Digital-to-Analog (DAC) Output

17

Reconstruction Filter

17

FDBK_IN Inputs

18

SYSCLK Inputs

19

Output Clock Drivers and 2× Frequency Multiplier

21

Harmonic Spur Reduction

21

Thermal Performance

23

Power-Up

24

Power-On Reset

24

Default Output Frequency on Power-Up

24

REVISION HISTORY

 

 

11/09—Rev. C to Rev. D

 

 

Added 64-Lead LFCSP (CP-64-7)

Universal

Changes to Serial Port Timing Specifications and

 

 

Propagation Delay Parameters

6

Added Exposed Paddle Notation to Figure 2

8

Changes to Power Supply Partitioning Section

25

Change to Serial Control Port Section

26

Changes to Figure 52

28

Added Exposed Paddle Notation to Outline Dimensions

38

Changes to Ordering Guide

39

7/09—Rev. B to Rev. C

 

 

Changes to Logic Outputs Parameter, Table 1

3

Changes to AVDD (Pin 25, Pin 26, Pin 29, and Pin 30)

25

Power Supply Partitioning

25

3.3 V Supplies

25

1.8 V Supplies

25

Serial Control Port

26

Serial Control Port Pin Descriptions

26

Operation of Serial Control Port

26

The Instruction Word (16 Bits)

27

MSB/LSB First Transfers

27

I/O Register Map

30

I/O Register Descriptions

32

Serial Port Configuration (Register 0x0000 to

 

Register 0x0005)

32

Power-Down and Reset (Register 0x0010 to

 

Register 0x0013)

32

System Clock (Register 0x0020 to Register 0x0022)

33

CMOS Output Divider (S-Divider) (Register 0x0100 to

 

Register 0x0106)

34

Frequency Tuning Word (Register 0x01A0 to

 

Register 0x01AD)

34

Doubler and Output Drivers (Register 0x0200 to

 

Register 0x0201)

36

Calibration (User-Accessible Trim) (Register 0x0400 to

 

Register 0x0410)

36

Harmonic Spur Reduction (Register 0x0500 to

 

Register 0x0509)

36

Outline Dimensions

38

Ordering Guide

39

6/09—Rev. A to Rev. B

 

Changes to Figure 40 and Direct Digital Synthesizer Section..

17

Changes to Figure 48

22

Changes to Table 11

30

Changes to Table 22 and Table 23

34

1/08—Rev. 0 to Rev. A

 

Changes to Table 1

3

Changes to Table 2

5

Changes to Table 4

8

Changes to Typical Performance Characteristics

10

Changes to Functional Description Section

19

Changes to Single-Ended CMOS Output Section

21

Changes to Harmonic Spur Reduction Section

21

Changes to Power Supply Partitioning Section

25

10/07—Revision 0: Initial Version

 

Rev. D Page 2 of 40

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Contents Applications FeaturesBasic Block Diagram General DescriptionTable of Contents Parameter Min Typ Max Unit Test Conditions/Comments SpecificationsDC Specifications Clock Output Drivers Total Power DissipationSystem Clock Input AC Specifications Parameter Min Typ Max Unit Test Conditions/CommentsAvss − ESD Caution Absolute Maximum RatingsThermal Resistance Parameter RatingPIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic DescriptionGND Avss ResetIoupdate OutbTypical Performance Characteristics Video BWAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Direct Digital Synthesizer DDS Theory of OperationOverview Solving this equation for FTW yields DIGITAL-TO-ANALOG DAC OutputReconstruction Filter 1024 Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter ResponseSysclk PLL Doubler Sysclk InputsFunctional Description Detail of Sysclk Differential Inputs Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core External Loop Filter Sysclk PLLOutput Clock Drivers and 2× Frequency Multiplier Harmonic Spur ReductionSpur Reduction Circuit Diagram Thermal Performance Thermal ParametersDefault Output Frequency on POWER-UP POWER-UPPOWER-ON Reset Power Supply Partitioning SuppliesOperation of Serial Control Port Serial Control PortSerial Control Port PIN Descriptions Read MSB/LSB First TransfersInstruction Word 16 Bits Operations are changed to LSB first orderSerial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10Parameter Description Register MAP PLLHSR-A Power-up default is defined by the start-up pins Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Register DescriptionsRegister 0x0020-N-Divider Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x0105-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0106-S-DividerRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x040C-DAC Full-Scale Current Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040D to Register 0x0410-ReservedRegister 0x0505-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0506-Spur BOutline Dimensions AD9912BCPZ1 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ-REEL71Rev. D Page 40
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