Analog Devices AD9912 specifications Power Supply Partitioning, Supplies

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AD9912

POWER SUPPLY PARTITIONING

The AD9912 features multiple power supplies, and their power consumption varies with its configuration. This section covers which power supplies can be grouped together and how the power consumption of each block varies with frequency.

The numbers quoted here are for comparison only. Refer to the Specifications section for exact numbers. With each group, use bypass capacitors of 1 μF in parallel with a 10 μF.

The recommendations here are for typical applications, and for these applications, there are four groups of power supplies:

3.3 V digital, 3.3 V analog, 1.8 V digital, and 1.8 V analog.

Applications demanding the highest performance may require additional power supply isolation.

Important: All power supply pins must receive power regardless of whether that block is used.

3.3 V SUPPLIES

DVDD_I/O (Pin 1) and AVDD3 (Pin 14)

Although one of these pins is analog and the other is digital, these two 3.3 V supplies can be grouped together. The power consumption on Pin 1 varies dynamically with serial port activity.

AVDD3 (Pin 37)

This is the CMOS driver supply. It can be either 1.8 V or 3.3 V, and its power consumption is a function of the output frequency and loading of OUT_CMOS (Pin 38).

If the CMOS driver is used at 3.3 V, this supply should be isolated from other 3.3 V supplies with a ferrite bead to avoid a spur at the output frequency. If the HSTL driver is not used, AVDD3 (Pin 37) can be connected (using a ferrite bead) to AVDD3 (Pin 46, Pin 47, and Pin 49). If the HSTL driver is used, connect AVDD3 (Pin 37) to Pin 1 and Pin 14, using a ferrite bead.

If the CMOS driver is used at 1.8 V, AVDD3 (Pin 37) can be connected to AVDD (Pin 36).

If the CMOS driver is not used, AVDD3 (Pin 37) can be tied directly to the 1.8 V AVDD (Pin 36) and the CMOS driver powered down using Register 0x0010.

AVDD3 (Pin 46, Pin 47, and Pin 49)

These are 3.3 V DAC power supplies that typically consume about 25 mA. At a minimum, a ferrite bead should be used to isolate these from other 3.3 V supplies, with a separate regulator being ideal.

1.8 V SUPPLIES

DVDD (Pin 3, Pin 5, and Pin 7)

These pins should be grouped together and isolated from the

1.8V AVDD supplies. For most applications, a ferrite bead provides sufficient isolation, but a separate regulator may be necessary for applications demanding the highest performance. The current consumption of this group increases from about 160 mA at a system clock of 700 MHz to about 205 mA at a system clock of 1 GHz. There is also a slight (~5%) increase as fOUT increases from 50 MHz to 400 MHz.

AVDD (Pin 11, Pin 19, Pin 23, Pin 24, Pin 36, Pin 42, Pin 44, and Pin 45)

These pins can be grouped together and should be isolated from other 1.8 V supplies. A separate regulator is recommended. At a minimum, a ferrite bead should be used for isolation.

AVDD (Pin 53)

This 1.8 V supply consumes about 40 mA. The supply can be run off the same regulator as the 1.8 V AVDD group, with a ferrite bead to isolate Pin 53 from the rest of the 1.8 V AVDD group. However, for applications demanding the highest performance, a separate regulator is recommended.

AVDD (Pin 25, Pin 26, Pin 29, and Pin 30)

These system clock PLL power pins should be grouped together and isolated from other 1.8 V AVDD supplies.

At a minimum, it is recommended that Pin 25 and Pin 30 be tied together and isolated from the aggregate AVDD 1.8 V supply with a ferrite bead. Likewise, Pin 26 and Pin 29 can also be tied together, with a ferrite bead isolating them from the same aggregate 1.8 V supply. The loop filter for the system clock PLL should directly connect to Pin 26 and Pin 29 (see Figure 46).

Applications demanding the highest performance may need to have these four pins powered by their on their own LDO.

If the system clock PLL is bypassed, the loop filter pin (Pin 31) should be pulled down to analog ground using a 1 kΩ resistor. Pin 25, Pin 26, Pin 29, and Pin 30 should be included in the large

1.8V AVDD power supply group. In this mode, isolation of these pins is not critical, and these pins consume almost no power.

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Contents Basic Block Diagram FeaturesApplications General DescriptionTable of Contents DC Specifications SpecificationsParameter Min Typ Max Unit Test Conditions/Comments System Clock Input Total Power DissipationClock Output Drivers Parameter Min Typ Max Unit Test Conditions/Comments AC SpecificationsAvss − Thermal Resistance Absolute Maximum RatingsESD Caution Parameter RatingInput Pin No Output Pin Type Mnemonic Description PIN Configuration and Function DescriptionsIoupdate ResetGND Avss OutbVideo BW Typical Performance CharacteristicsAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Overview Theory of OperationDirect Digital Synthesizer DDS Reconstruction Filter DIGITAL-TO-ANALOG DAC OutputSolving this equation for FTW yields 1024 DAC Spectrum vs. Reconstruction Filter Response Fdbkin InputsFunctional Description Sysclk InputsSysclk PLL Doubler Sysclk PLL multiplier has a 1 GHz VCO at its core Sysclk PLL MultiplierDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLLHarmonic Spur Reduction Output Clock Drivers and 2× Frequency MultiplierSpur Reduction Circuit Diagram Thermal Parameters Thermal PerformancePOWER-ON Reset POWER-UPDefault Output Frequency on POWER-UP Supplies Power Supply PartitioningSerial Control Port PIN Descriptions Serial Control PortOperation of Serial Control Port Instruction Word 16 Bits MSB/LSB First TransfersRead Operations are changed to LSB first orderI15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB FirstParameter Description PLL Register MAPHSR-A Register 0x0010-Power-Down and Enable Register 0x0000-Serial Port ConfigurationPower-up default is defined by the start-up pins Register DescriptionsRegister 0x0013-Reset Not Autoclearing Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-DividerRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x0201-CMOS Driver Register 0x0200-HSTL DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-ReservedRegister 0x0504-Spur a Register 0x0503-Spur aRegister 0x0505-Spur B Register 0x0506-Spur BOutline Dimensions Ordering Guide Model Temperature Range Package Description Package OptionAD9912BCPZ1 AD9912BCPZ-REEL71Rev. D Page 40
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