Analog Devices AD9912 GND Avss, Outb, Outcmos, Fdbkinb, Dacrset, Dacoutb, Pwrdown, Reset, Csb

Page 9

 

 

 

 

AD9912

 

 

 

 

 

 

 

 

 

 

 

Input/

 

 

 

Pin No.

Output

Pin Type

Mnemonic

Description

32

I

1.8 V CMOS

CLKMODESEL

Clock Mode Select. Set to GND when connecting a crystal to the system

 

 

 

 

clock input (Pin 27 and Pin 28). Pull up to 1.8 V when using either an

 

 

 

 

oscillator or an external clock source. This pin can be left unconnected

 

 

 

 

when the system clock PLL is bypassed. (See the SYSCLK Inputs section for

 

 

 

 

details on the use of this pin.)

33, 39, 43, 52

O

GND

AVSS

Analog Ground. Connect to ground.

34

O

1.8 V HSTL

OUTB

Complementary HSTL Output. See the Specifications and Primary 1.8 V

 

 

 

 

Differential HSTL Driver sections for details.

35

O

1.8 V HSTL

OUT

HSTL Output. See the Specifications and Primary 1.8 V Differential HSTL

 

 

 

 

Driver sections for details.

37

I

Power

AVDD3

Analog Supply for CMOS Output Driver. This pin is normally 3.3 V but can

 

 

 

 

be 1.8 V. This pin should be powered even if the CMOS driver is not used.

 

 

 

 

See the Power Supply Partitioning section for power supply partitioning.

38

O

3.3 V CMOS

OUT_CMOS

CMOS Output. See the Specifications section and the Output Clock Drivers

 

 

 

 

and 2× Frequency Multiplier section. This pin is 1.8 V CMOS if Pin 37 is set

 

 

 

 

to 1.8 V.

40

I

Differential

FDBK_INB

Complementary Feedback Input. When using the HSTL and CMOS outputs,

 

 

input

 

this pin is connected to the filtered DAC_OUTB output. This internally

 

 

 

 

biased input is typically ac-coupled, and when configured as such, can

 

 

 

 

accept any differential signal whose single-ended swing is at least 400 mV.

41

I

Differential

FDBK_IN

Feedback Input. In standard operating mode, this pin is connected to the

 

 

input

 

filtered DAC_OUT output.

48

O

Current set

DAC_RSET

DAC Output Current Setting Resistor. Connect a resistor (usually 10 k Ω)

 

 

resistor

 

from this pin to GND. See the Digital-to-Analog (DAC) Output section.

50

O

Differential

DAC_OUT

DAC Output. This signal should be filtered and sent back on-chip through

 

 

output

 

the FDBK_IN input. This pin has an internal 50 Ω pull-down resistor.

51

O

Differential

DAC_OUTB

Complementary DAC Output. This signal should be filtered and sent back

 

 

output

 

on-chip through the FDBK_INB input. This pin has an internal 50 Ω pull-

 

 

 

 

down resistor.

56, 57

 

Power

DVSS

Digital Ground. Connect to ground.

58

I

3.3 V CMOS

PWRDOWN

Power-Down. When this active high pin is asserted, the device becomes

 

 

 

 

inactive and enters the full power-down state. This pin has an internal

 

 

 

 

50 kΩ pull-down resistor.

59

I

3.3 V CMOS

RESET

Chip Reset. When this active high pin is asserted, the chip goes into reset.

 

 

 

 

Note that on power-up, a 10 μs reset pulse is internally generated when

 

 

 

 

the power supplies reach a threshold and stabilize. This pin should be

 

 

 

 

grounded with a 10 kΩ resistor if not used.

60

I

3.3 V CMOS

IO_UPDATE

I/O Update. A logic transition from 0 to 1 on this pin transfers data from the

 

 

 

 

I/O port registers to the control registers (see the Write section). This pin

 

 

 

 

has an internal 50 kΩ pull-down resistor.

61

I

3.3 V CMOS

CSB

Chip Select. Active low. When programming a device, this pin must be held

 

 

 

 

low. In systems where more than one AD9912 is present, this pin enables

 

 

 

 

individual programming of each AD9912. This pin has an internal 100 kΩ

 

 

 

 

pull-up resistor.

62

O

3.3 V CMOS

SDO

Serial Data Output. When the device is in 3-wire mode, data is read on this

 

 

 

 

pin. There is no internal pull-up/pull-down resistor on this pin.

63

I/O

3.3 V CMOS

SDIO

Serial Data Input/Output. When the device is in 3-wire mode, data is

 

 

 

 

written via this pin. In 2-wire mode, data reads and writes both occur on

 

 

 

 

this pin. There is no internal pull-up/pull-down resistor on this pin.

64

I

3.3 V CMOS

SCLK

Serial Programming Clock. Data clock for serial programming. This pin has

 

 

 

 

an internal 50 kΩ pull-down resistor.

Exposed Die Pad

O

GND

EPAD

Analog Ground. The exposed die pad on the bottom of the package

 

 

 

 

provides the analog ground for the part; this exposed pad must be

 

 

 

 

connected to ground for proper operation.

Rev. D Page 9 of 40

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Contents Basic Block Diagram FeaturesApplications General DescriptionTable of Contents Specifications DC SpecificationsParameter Min Typ Max Unit Test Conditions/Comments Total Power Dissipation System Clock InputClock Output Drivers Parameter Min Typ Max Unit Test Conditions/Comments AC SpecificationsAvss − Thermal Resistance Absolute Maximum RatingsESD Caution Parameter RatingInput Pin No Output Pin Type Mnemonic Description PIN Configuration and Function DescriptionsIoupdate ResetGND Avss OutbVideo BW Typical Performance CharacteristicsAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Theory of Operation OverviewDirect Digital Synthesizer DDS Reconstruction Filter DIGITAL-TO-ANALOG DAC OutputSolving this equation for FTW yields 1024 DAC Spectrum vs. Reconstruction Filter Response Fdbkin InputsSysclk Inputs Functional DescriptionSysclk PLL Doubler Sysclk PLL multiplier has a 1 GHz VCO at its core Sysclk PLL MultiplierDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLLHarmonic Spur Reduction Output Clock Drivers and 2× Frequency MultiplierSpur Reduction Circuit Diagram Thermal Parameters Thermal PerformancePOWER-UP POWER-ON ResetDefault Output Frequency on POWER-UP Supplies Power Supply PartitioningSerial Control Port Serial Control Port PIN DescriptionsOperation of Serial Control Port Instruction Word 16 Bits MSB/LSB First TransfersRead Operations are changed to LSB first orderI15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB FirstParameter Description PLL Register MAPHSR-A Register 0x0010-Power-Down and Enable Register 0x0000-Serial Port ConfigurationPower-up default is defined by the start-up pins Register DescriptionsRegister 0x0013-Reset Not Autoclearing Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-DividerRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x0201-CMOS Driver Register 0x0200-HSTL DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-ReservedRegister 0x0504-Spur a Register 0x0503-Spur aRegister 0x0505-Spur B Register 0x0506-Spur BOutline Dimensions Ordering Guide Model Temperature Range Package Description Package OptionAD9912BCPZ1 AD9912BCPZ-REEL71Rev. D Page 40
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