Analog Devices AD9912 specifications Absolute Phase Noise Using Hstl Driver

Page 11

AD9912

 

10

 

 

CARRIER:

 

20.1MHz

 

 

0

 

 

 

 

 

 

 

SFDR:

 

–95dBc

 

 

–10

 

 

FREQ. SPAN:

 

500kHz

 

 

 

 

RESOLUTION BW:

300Hz

 

 

 

 

 

 

(dBm)

–20

 

 

VIDEO BW:

 

1kHz

 

–30

 

 

 

 

 

 

–40

 

 

 

 

 

 

POWER

 

 

 

 

 

 

–50

 

 

 

 

 

 

–60

 

 

 

 

 

 

SIGNAL

 

 

 

 

 

 

–70

 

 

 

 

 

 

–80

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–90

 

 

 

 

 

 

 

–100

 

 

 

 

 

 

 

–110

 

 

 

 

 

-009

 

19.85

19.95

20.05

20.15

20.25

20.35

 

06763

 

 

 

FREQUENCY (MHz)

 

 

 

–80

 

–90

(dBc/Hz)

–100

–110

NOISE

–120

PHASE

–130

 

 

–140

 

–150

 

–160

 

100

RMS JITTER (100Hz TO 40MHz): 99MHz: 413fs

399MHz: 222fs

399MHz

99MHz

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

06763-012

Figure 9. Narrow-Band SFDR at 20.1 MHz,

SYSCLK = 1 GHz (SYSCLK PLL Bypassed)

 

10

 

 

CARRIER:

201.1MHz

 

 

0

 

 

 

 

 

 

SFDR:

–91dBc

 

 

–10

 

 

FREQ. SPAN:

500kHz

 

 

 

 

 

RESOLUTION BW: 300Hz

 

 

 

 

 

 

 

 

(dBm)

–20

 

 

VIDEO BW:

1kHz

 

 

–30

 

 

 

 

 

 

 

 

 

 

 

 

 

POWER

–40

 

 

 

 

 

 

–50

 

 

 

 

 

 

 

 

 

 

 

 

 

SIGNAL

–60

 

 

 

 

 

 

–70

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–80

 

 

 

 

 

 

 

–90

 

 

 

 

 

 

 

–100

 

 

 

 

 

 

 

–110

 

 

 

 

 

-010

 

200.85

200.95

201.05

201.15

201.25

201.35

 

06763

 

 

 

FREQUENCY (MHz)

 

 

Figure 10. Narrow-Band SFDR at 201.1 MHz,

SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)

 

10

 

 

CARRIER:

398.7MHz

 

 

0

 

 

 

 

 

 

SFDR:

–86dBc

 

 

–10

 

 

FREQ. SPAN:

500kHz

 

 

 

 

 

RESOLUTION BW: 300Hz

 

 

 

 

 

 

 

 

(dBm)

–20

 

 

VIDEO BW:

1kHz

 

 

–30

 

 

 

 

 

 

–40

 

 

 

 

 

 

POWER

 

 

 

 

 

 

–50

 

 

 

 

 

 

–60

 

 

 

 

 

 

SIGNAL

 

 

 

 

 

 

–70

 

 

 

 

 

 

–80

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–90

 

 

 

 

 

 

 

–100

 

 

 

 

 

 

 

–110

 

 

 

 

 

-011

 

398.45

398.55

398.65

398.75

398.85

398.95

 

06763

 

 

 

FREQUENCY (MHz)

 

 

Figure 11. Narrow-Band SFDR at 398.7 MHz,

SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)

Figure 12. Absolute Phase Noise Using HSTL Driver,

SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)

 

–80

 

 

RMS JITTER (12kHz TO 20MHz):

 

 

 

 

 

 

 

–90

 

 

99MHz:

0.98ps

 

 

 

 

 

 

399MHz: 0.99ps

 

 

 

 

 

 

 

 

 

 

(dBc/Hz)

–100

 

 

 

 

 

 

 

 

–110

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOISE

–120

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHASE

–130

 

 

 

 

 

399MHz

 

–140

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–150

 

 

 

 

 

99MHz

 

 

 

 

 

 

 

 

 

 

 

–160

 

 

 

 

 

 

 

-013

 

10

100

1k

10k

100k

1M

10M

100M

 

06763

 

 

 

FREQUENCY OFFSET (Hz)

 

 

Figure 13. Absolute Phase Noise Using HSTL Driver,

SYSCLK = 1 GHz (SYSCLK PLL Driven by Rohde & Schwarz SMA100 Signal

Generator at 83.33 MHz )

 

–80

 

 

RMS JITTER (12kHz TO 20MHz):

 

 

 

 

 

 

 

–90

 

 

99MHz:

1.41ps

 

 

 

 

 

 

399MHz: 1.46ps

 

 

 

 

 

 

 

 

 

 

(dBc/Hz)

–100

 

 

 

 

 

 

 

 

–110

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOISE

–120

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHASE

–130

 

 

 

 

 

399MHz

 

 

 

 

 

 

 

 

–140

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–150

 

 

 

 

 

99MHz

 

 

 

 

 

 

 

 

 

 

 

–160

 

 

 

 

 

 

 

-014

 

10

100

1k

10k

100k

1M

10M

100M

 

06763

 

 

 

FREQUENCY OFFSET (Hz)

 

 

Figure 14. Absolute Phase Noise Using HSTL Driver,

SYSCLK = 1 GHz (SYSCLK PLL Driven by Rohde & Schwarz SMA100 Signal

Generator at 25 MHz )

Rev. D Page 11 of 40

Image 11
Contents General Description FeaturesBasic Block Diagram ApplicationsTable of Contents Parameter Min Typ Max Unit Test Conditions/Comments SpecificationsDC Specifications Clock Output Drivers Total Power DissipationSystem Clock Input Parameter Min Typ Max Unit Test Conditions/Comments AC SpecificationsAvss − Parameter Rating Absolute Maximum RatingsThermal Resistance ESD CautionInput Pin No Output Pin Type Mnemonic Description PIN Configuration and Function DescriptionsOutb ResetIoupdate GND AvssVideo BW Typical Performance CharacteristicsAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Direct Digital Synthesizer DDS Theory of OperationOverview 1024  DIGITAL-TO-ANALOG DAC OutputReconstruction Filter Solving this equation for FTW yieldsDAC Spectrum vs. Reconstruction Filter Response Fdbkin InputsSysclk PLL Doubler Sysclk InputsFunctional Description External Loop Filter Sysclk PLL Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core Detail of Sysclk Differential InputsHarmonic Spur Reduction Output Clock Drivers and 2× Frequency MultiplierSpur Reduction Circuit Diagram Thermal Parameters Thermal PerformanceDefault Output Frequency on POWER-UP POWER-UPPOWER-ON Reset Supplies Power Supply PartitioningOperation of Serial Control Port Serial Control PortSerial Control Port PIN Descriptions Operations are changed to LSB first order MSB/LSB First TransfersInstruction Word 16 Bits ReadI15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB FirstParameter Description PLL Register MAPHSR-A Register Descriptions Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Power-up default is defined by the start-up pinsRegister 0x0021-Reserved Register 0x0022-PLL Parameters Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0020-N-DividerRegister 0x0106-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0105-S-DividerRegister 0x01AC-Phase Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AB-FTW0 Frequency Tuning WordRegister 0x040D to Register 0x0410-Reserved Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040C-DAC Full-Scale CurrentRegister 0x0506-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0505-Spur BOutline Dimensions AD9912BCPZ-REEL71 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ1Rev. D Page 40