Analog Devices AD9912 specifications Cmos Output Driver Waveform @ 3.3

Page 14

AD9912

 

650

 

 

600

 

(mV)

 

 

AMPLITUDE

550

 

 

 

 

500

 

 

450 0

NOM SKEW 25°C, 1.8V SUPPLY

WORST CASE (SLOW SKEW 90°C, 1.7V SUPPLY)

200

400

600

 

FREQUENCY (MHz)

 

800

06763-021

 

0.6

 

 

 

 

 

 

 

0.4

 

 

 

 

 

 

(V)

0.2

 

 

 

 

 

 

 

 

 

 

 

 

 

AMPLITUDE

0

 

 

 

 

 

 

 

 

 

FREQUENCY = 600MHz

 

 

–0.2

 

 

tRISE (20%→80%) = 104ps

 

 

 

 

 

 

 

 

 

 

 

tFALL (80%→20%) = 107ps

 

 

 

 

 

 

V p-p = 1.17V DIFF.

 

 

 

–0.4

 

 

DUTY CYCLE = 50%

 

 

 

 

 

 

 

 

 

 

–0.6

 

 

 

 

 

-024

 

0

0.5

1.0

1.5

2.0

2.5

 

06763

 

 

 

TIME (ns)

 

 

Figure 27. HSTL Output Driver Single-Ended Peak-to-Peak Amplitude vs.

Figure 30. Typical HSTL Output Waveform, Nominal Conditions,

Toggle Rate (100 Ω Across Differential Pair)

DC-Coupled, Differential Probe Across 100 Ω load

AMPLITUDE (V)

2.5

2.0

1.5

1.0

0.5NOM SKEW 25°C, 1.8V SUPPLY (20pF) WORST CASE (SLOW SKEW 90°C, 1.7V SUPPLY (20pF))

0 0

 

 

 

 

 

10

20

30

 

 

 

FREQUENCY (MHz)

 

40

 

 

1.8

 

 

 

 

 

 

 

 

1.6

 

 

 

 

 

 

 

 

1.4

 

 

 

 

 

 

 

 

1.2

 

 

 

 

 

 

 

(V)

1.0

 

 

 

 

 

 

 

AMPLITUDE

 

 

 

 

 

 

 

0.8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.6

 

 

FREQUENCY = 20MHz

 

 

 

 

0.4

 

 

tRISE (20%→80%) = 5.5ns

 

 

 

 

 

 

tFALL (80%→20%) = 5.9ns

 

 

 

 

 

 

 

 

 

 

 

0.2

 

 

V p-p = 1.8V

 

 

 

 

 

 

 

DUTY CYCLE = 53%

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

06763-022

 

–0.2

20

40

60

80

100

06763-025

 

0

 

 

 

 

TIME (ns)

 

 

Figure 28. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate

Figure 31. Typical CMOS Output Driver Waveform (@ 1.8 V),

(AVDD3 = 1.8 V) with 20 pF Load

Nominal Conditions, Estimated Capacitance = 5 pF

AMPLITUDE (V)

3.5

3.0

2.5

2.0

1.5

NOM SKEW 25°C, 1.8V SUPPLY (20pF)

1.0WORST CASE (SLOW SKEW 90°C, 3.0V SUPPLY (20pF))

0.5

0

0

50

100

 

FREQUENCY (MHz)

150

 

3.3

 

 

 

 

 

 

 

2.8

 

 

 

 

 

 

(V)

2.3

 

 

 

 

 

 

 

 

 

tRISE (20%→80%) = 2.25ns

 

 

AMPLITUDE

1.3

 

 

 

 

 

1.8

 

 

 

 

 

 

 

 

 

 

FREQUENCY = 40MHz

 

 

 

0.8

 

 

tFALL (80%→20%) = 2.6ns

 

 

 

 

 

V p-p = 3.3V

 

 

 

 

 

 

 

DUTY CYCLE = 52%

 

 

 

0.3

 

 

 

 

 

 

06763-023

–0.2 0

10

20

30

40

50

06763-026

 

 

 

TIME (ns)

 

 

 

 

 

 

 

 

 

Figure 29. CMOS Output Driver Peak-to-Peak Amplitude vs. Toggle Rate

Figure 32. CMOS Output Driver Waveform (@ 3.3 V),

(AVDD3 = 3.3 V) with 20 pF Load

Nominal Conditions, Estimated Capacitance = 5 pF

Rev. D Page 14 of 40

Image 14
Contents Applications FeaturesBasic Block Diagram General DescriptionTable of Contents Parameter Min Typ Max Unit Test Conditions/Comments SpecificationsDC Specifications Clock Output Drivers Total Power DissipationSystem Clock Input AC Specifications Parameter Min Typ Max Unit Test Conditions/CommentsAvss − ESD Caution Absolute Maximum RatingsThermal Resistance Parameter RatingPIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic DescriptionGND Avss ResetIoupdate OutbTypical Performance Characteristics Video BWAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Direct Digital Synthesizer DDS Theory of OperationOverview Solving this equation for FTW yields DIGITAL-TO-ANALOG DAC OutputReconstruction Filter 1024 Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter ResponseSysclk PLL Doubler Sysclk InputsFunctional Description Detail of Sysclk Differential Inputs Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core External Loop Filter Sysclk PLLOutput Clock Drivers and 2× Frequency Multiplier Harmonic Spur ReductionSpur Reduction Circuit Diagram Thermal Performance Thermal ParametersDefault Output Frequency on POWER-UP POWER-UPPOWER-ON Reset Power Supply Partitioning SuppliesOperation of Serial Control Port Serial Control PortSerial Control Port PIN Descriptions Read MSB/LSB First TransfersInstruction Word 16 Bits Operations are changed to LSB first orderSerial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10Parameter Description Register MAP PLLHSR-A Power-up default is defined by the start-up pins Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Register DescriptionsRegister 0x0020-N-Divider Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x0105-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0106-S-DividerRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x040C-DAC Full-Scale Current Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040D to Register 0x0410-ReservedRegister 0x0505-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0506-Spur BOutline Dimensions AD9912BCPZ1 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ-REEL71Rev. D Page 40