Analog Devices AD9912 specifications Spur Reduction Circuit Diagram

Page 22

AD9912

Although the worst spurs tend to be harmonic in origin, the fact that the DAC is part of a sampled system results in the possibility of spurs appearing in the output spectrum that are not harmoni- cally related to the fundamental. For example, if the DAC is sampled at 1 GHz and generates an output sinusoid of 170 MHz, the fifth harmonic would normally be at 850 MHz. However, because of the sampling process, this spur appears at 150 MHz, only 20 MHz away from the fundamental. Therefore, when attempting to reduce DAC spurs it is important to know the actual location of the harmonic spur in the DAC output spectrum based on the DAC sample rate so that its harmonic number can be reduced.

The mechanics of performing harmonic spur reduction is shown in Figure 48. It essentially consists of two additional DDS cores operating in parallel with the original DDS. This enables the user to reduce two different harmonic spurs from the second to the 15th with nine bits of phase offset control (±π) and eight bits of amplitude control.

The dynamic range of the cancellation signal is further aug- mented by a gain bit associated with each channel. When this bit is set, the magnitude of the cancellation signal is doubled by employing a 1-bit left-shift of the data. However, the shift operation reduces the granularity of the cancellation signal magnitude. The full-scale amplitude of a cancellation spur is approximately −60 dBc when the gain bit is a Logic 0 and approximately −54 dBc when the gain bit is a Logic 1.

The procedure for tuning the spur reduction is as follows:

1.Determine which offending harmonic spur to reduce and its amplitude. Enter that harmonic number into Bit 0 to Bit 3 of Register 0x0500/Register 0x0505.

2.Turn off the fundamental by setting Bit 7 of Register 0x0013 and enable the SpurKiller channel by setting Bit 7 of Register 0x0500/Register 0x0505.

3.Adjust the amplitude of the SpurKiller channel so that it matches the amplitude of the offending spur.

4.Turn the fundamental on by clearing Bit 7 of Register 0x0013.

5.Adjust the phase of the SpurKiller channel so that maximum interference is achieved.

Note that the SpurKiller setting is sensitive to the loading of the DAC output pins, and that a DDS reset is required if a SpurKiller channel is turned off. The DDS can be reset by setting Bit 0 of Register 0x0012, and resetting the part is not necessary.

The performance improvement offered by this technique varies widely and depends on the conditions used. Given this extreme variability, it is impossible to define a meaningful specification to guarantee SpurKiller performance. Current data indicate that a 6 dB to 8 dB improvement is possible for a given output frequency using a common setting over process, temperature, and voltage. There are frequencies, however, where a common setting can result in much greater improvement. Manually adjusting the SpurKiller settings on individual parts can result in more than 30 dB of spurious performance improvement.

 

 

 

 

 

 

DDS

DDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHASE

 

 

 

SPUR

 

 

 

 

 

 

 

 

OFFSET

 

 

 

DAC I-SET

DAC_RSET

 

 

48-BIT ACCUMULATOR

 

 

 

 

CANCELLATION

 

 

 

 

 

 

 

REGISTERS

 

 

 

48

 

 

 

 

 

 

ENABLE

 

 

 

 

 

 

14

 

 

 

AND LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

48-BIT

14

48

 

 

19

19

ANGLE TO

14

 

 

 

 

FREQUENCY

 

 

0

 

 

DAC_OUT

D

Q

AMPLITUDE

14

DAC

TURNING WORD

 

 

 

 

 

 

 

 

 

 

 

CONVERSION

 

 

 

(14-BIT)

 

(FTW)

 

 

 

 

 

 

 

1

 

DAC_OUTB

 

 

 

 

 

 

 

 

 

 

 

SYSCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

2-CHANNEL

 

 

 

 

 

 

 

 

CH1 HARMONIC NUMBER

 

HARMONIC

 

 

 

HEADROOM

 

 

 

 

 

 

FREQUENCY

 

 

 

CORRECTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CH1 CANCELLATION PHASE OFFSET

9

 

GENERATOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CH1

 

SHIFT

1

 

 

 

 

 

CH2 HARMONIC NUMBER

4

 

 

 

 

 

 

 

CH1 GAIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CH2 CANCELLATION PHASE OFFSET

9

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

CH2

 

SHIFT

 

1

 

 

 

 

CH1 CANCELLATION MAGNITUDE

8

 

 

 

 

 

 

 

CH2 GAIN

 

 

 

 

 

 

 

 

 

 

 

 

CH2 CANCELLATION MAGNITUDE

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HARMONIC SPUR CANCELLATION

06763-040

Figure 48. Spur Reduction Circuit Diagram

Rev. D Page 22 of 40

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Contents Applications FeaturesBasic Block Diagram General DescriptionTable of Contents DC Specifications SpecificationsParameter Min Typ Max Unit Test Conditions/Comments System Clock Input Total Power DissipationClock Output Drivers AC Specifications Parameter Min Typ Max Unit Test Conditions/CommentsAvss − ESD Caution Absolute Maximum RatingsThermal Resistance Parameter RatingPIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic DescriptionGND Avss ResetIoupdate OutbTypical Performance Characteristics Video BWAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Overview Theory of OperationDirect Digital Synthesizer DDS Solving this equation for FTW yields DIGITAL-TO-ANALOG DAC OutputReconstruction Filter 1024 Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter ResponseFunctional Description Sysclk InputsSysclk PLL Doubler Detail of Sysclk Differential Inputs Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core External Loop Filter Sysclk PLLOutput Clock Drivers and 2× Frequency Multiplier Harmonic Spur ReductionSpur Reduction Circuit Diagram Thermal Performance Thermal ParametersPOWER-ON Reset POWER-UPDefault Output Frequency on POWER-UP Power Supply Partitioning SuppliesSerial Control Port PIN Descriptions Serial Control PortOperation of Serial Control Port Read MSB/LSB First TransfersInstruction Word 16 Bits Operations are changed to LSB first orderSerial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10Parameter Description Register MAP PLLHSR-A Power-up default is defined by the start-up pins Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Register DescriptionsRegister 0x0020-N-Divider Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x0105-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0106-S-DividerRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x040C-DAC Full-Scale Current Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040D to Register 0x0410-ReservedRegister 0x0505-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0506-Spur BOutline Dimensions AD9912BCPZ1 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ-REEL71Rev. D Page 40
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