Analog Devices AD9912 specifications Register MAP, Pll

Page 30

AD9912

I/O REGISTER MAP

All address and bit locations that are left blank in Table 12 are unused.

Table 12.

Addr

Type1

 

 

 

 

 

 

 

 

 

 

 

 

Default

(Hex)

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

 

Bit 2

 

Bit 1

Bit 0

(Hex)

Serial port configuration and part identification

 

 

 

 

 

 

 

 

 

 

 

0x0000

 

Serial

SDO

LSB first

Soft

Long

 

Long

 

Soft reset

 

LSB first

SDO

0x18

 

 

config.

active

(buffered)

reset

instruction

 

instruction

 

 

 

(buffered)

active

 

0x0001

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

0x00

0x0002

RO

Part ID

 

 

 

Part ID

 

 

 

 

 

0x02

0x0003

RO

 

 

 

 

 

 

 

 

 

 

 

 

0x09

0x0004

 

Serial

 

 

 

 

 

 

 

 

 

 

Read buffer

0x00

 

 

options

 

 

 

 

 

 

 

 

 

 

register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x0005

AC

 

 

 

 

 

 

 

 

 

 

 

Register

0x00

 

 

 

 

 

 

 

 

 

 

 

 

 

update

 

Power-down and reset

 

 

 

 

 

 

 

 

 

 

 

 

0x0010

 

Power-

PD HSTL

Enable

Enable

PD

 

 

 

 

Full PD

Digital PD

0xC0 or

 

 

down and

driver

CMOS

output

SYSCLK

 

 

 

 

 

 

0xD0

 

 

enable

 

driver

doubler

PLL

 

 

 

 

 

 

 

0x0011

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

0x00

0x0012

M, AC

Reset

 

 

 

 

 

 

 

 

 

 

DDS reset

0x00

0x0013

M

 

PD fund

 

 

 

 

S-div/2

 

 

 

S-divider

 

0x00

 

 

 

DDS

 

 

 

 

reset

 

 

 

reset

 

 

System clock

 

 

 

 

 

 

 

 

 

 

 

 

 

0x0020

 

N-divider

 

 

 

 

 

 

N-divider, Bits[4:0]

 

0x12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x0021

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

0x00

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x0022

 

PLL

VCO auto

 

 

 

 

2× refer-

 

VCO range

 

Charge pump current,

0x04

 

 

parameters

range

 

 

 

 

ence

 

 

 

Bits[1:0]

 

CMOS output divider (S-divider)

 

 

 

 

 

 

 

 

 

 

 

 

0x0100

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

0x30

0x0101

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

0x00

to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x0103

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x0104

 

S-divider

 

 

 

S-divider, Bits[15:0]

 

 

 

 

 

0x00

and

 

 

 

 

 

LSB: Register 0x0104

 

 

 

 

 

 

0x0105

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x0106

 

 

Falling

 

 

 

 

 

 

 

 

 

S-divider/2

0x01

 

 

 

edge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

triggered

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Frequency tuning word

 

 

 

 

 

 

 

 

 

 

 

 

0x01A0

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

0x00

to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x01A5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x01A6

M

FTW0

 

 

 

FTW0, Bits[47:0]

 

 

 

 

 

0x00

 

 

(frequency

 

 

 

LSB: Register 0x01A6

 

 

 

 

 

 

0x01A7

M

 

 

 

 

 

 

 

 

0x00

tuning

 

 

 

 

 

 

 

 

 

 

 

0x01A8

M

 

 

 

 

 

 

 

 

 

 

 

0x00

word)

 

 

 

 

 

 

 

 

 

 

 

0x01A9

M

 

 

 

 

 

 

 

 

 

 

 

0x00

 

 

 

 

 

 

 

 

 

 

 

 

0x01AA

M

 

 

 

 

 

 

 

 

 

 

 

 

Start-up

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cond.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x01AB

M

 

 

 

 

 

 

 

 

 

 

 

 

Start-up

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cond.

0x01AC

M

Phase

 

 

 

DDS phase word, Bits[7:0]

 

 

0x00

0x01AD

M

 

 

 

 

 

 

DDS phase word, Bits[13:8]

 

 

0x00

Doubler and output drivers

 

 

 

 

 

 

 

 

 

 

 

 

0x0200

 

HSTL driver

 

 

 

OPOL

 

 

 

 

HSTL output doubler,

0x05

 

 

 

 

 

 

(polarity)

 

 

 

 

Bits[1:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x0201

 

CMOS driver

 

 

 

 

 

 

 

 

 

 

CMOS mux

0x00

Rev. D Page 30 of 40

Page 29 Page 31
Image 30
Page 29 Page 31
Contents Applications FeaturesBasic Block Diagram General DescriptionTable of Contents Specifications DC SpecificationsParameter Min Typ Max Unit Test Conditions/Comments Total Power Dissipation System Clock InputClock Output Drivers AC Specifications Parameter Min Typ Max Unit Test Conditions/CommentsAvss − ESD Caution Absolute Maximum RatingsThermal Resistance Parameter RatingPIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic DescriptionGND Avss ResetIoupdate OutbTypical Performance Characteristics Video BWAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Theory of Operation OverviewDirect Digital Synthesizer DDS Solving this equation for FTW yields DIGITAL-TO-ANALOG DAC OutputReconstruction Filter 1024 Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter ResponseSysclk Inputs Functional DescriptionSysclk PLL Doubler Detail of Sysclk Differential Inputs Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core External Loop Filter Sysclk PLLOutput Clock Drivers and 2× Frequency Multiplier Harmonic Spur ReductionSpur Reduction Circuit Diagram Thermal Performance Thermal ParametersPOWER-UP POWER-ON ResetDefault Output Frequency on POWER-UP Power Supply Partitioning SuppliesSerial Control Port Serial Control Port PIN DescriptionsOperation of Serial Control Port Read MSB/LSB First TransfersInstruction Word 16 Bits Operations are changed to LSB first orderSerial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10Parameter Description Register MAP PLLHSR-A Power-up default is defined by the start-up pins Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Register DescriptionsRegister 0x0020-N-Divider Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x0105-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0106-S-DividerRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x040C-DAC Full-Scale Current Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040D to Register 0x0410-ReservedRegister 0x0505-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0506-Spur BOutline Dimensions AD9912BCPZ1 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ-REEL71Rev. D Page 40
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