Analog Devices AD9912 specifications MSB/LSB First Transfers, Instruction Word 16 Bits, Read

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Read

If the instruction word is for a read operation (I15 = 1), the next N × 8 SCLK cycles clock out the data from the address specified in the instruction word, where N is 1, 2, 3, or 4, as determined by [W1:W0]. In this case, 4 is used for streaming mode where four or more words are transferred per read. The data readback is valid on the falling edge of SCLK.

The default mode of the AD9912 serial control port is bidirec- tional mode, and the data readback appears on the SDIO pin. It is possible to set the AD9912 to unidirectional mode by writing to the SDO active bit (Register 0x0000, Bit 0 = 1), and in that mode, the requested data appears on the SDO pin.

By default, a read request reads the register value that is cur- rently in use by the AD9912. However, setting Register 0x0004, Bit 0 = 1 causes the buffered registers to be read instead. The buffered registers are the ones that take effect during the next I/O update.

AD9912

Bits[A12:A0] select the address within the register map that is written to or read from during the data transfer portion of the communications cycle. The AD9912 uses all of the 13-bit address space. For multibyte transfers, this address is the starting byte address.

Table 9. Byte Transfer Count

 

 

Bytes to Transfer

W1

W0

(Excluding the 2-Byte Instruction)

 

 

 

0

0

1

0

1

2

1

0

3

1

1

Streaming mode

MSB/LSB FIRST TRANSFERS

The AD9912 instruction word and byte data can be MSB first or LSB first. The default for the AD9912 is MSB first. The LSB first mode can be enabled by writing a 1 to the LSB first bit in the serial configuration register and then issuing an I/O update. Immediately after the LSB first bit is set, all serial control port

SCLK SDIO SDO CSB

SERIAL CONTROL PORT

REGISTER BUFFERS

UPDATE

REGISTERS

TOGGLE IO_UPDATE PIN

CONTROL REGISTERS

AD9912

CORE

06763-042

operations are changed to LSB first order.

When MSB first mode is active, the instruction and data bytes must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes must follow in order from high address to low address.

Figure 50. Relationship Between Serial Control Port Register Buffers and

Control Registers of the AD9912

The AD9912 uses Register 0x0000 to Register 0x0509. Although the AD9912 serial control port allows both 8-bit and 16-bit instructions, the 8-bit instruction mode provides access to five address bits (A4 to A0) only, which restricts its use to Address Space 0x00 to Address Space 0x31. The AD9912 defaults to 16-bit instruction mode on power-up, and the 8-bit instruction mode is not supported.

THE INSTRUCTION WORD (16 BITS)

The MSB of the instruction word is R/W, which indicates whether the instruction is a read or a write. The next two bits, [W1:W0], are the transfer length in bytes. The final 13 bits are the address ([A12:A0]) at which to begin the read or write operation.

For a write, the instruction word is followed by the number of bytes of data indicated by Bits[W1:W0], which is interpreted according to Table 9.

In MSB first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle.

When LSB first = 1 (LSB first), the instruction and data bytes must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial control port internal byte address generator increments for each byte of the multibyte transfer cycle.

The AD9912 serial control port register address decrements from the register address just written toward 0x0000 for multibyte I/O operations if the MSB first mode is active (default). If the LSB first mode is active, the serial control port register address increments from the address just written toward 0x1FFF for multibyte I/O operations.

Unused addresses are not skipped during multibyte I/O operations. The user should write the default value to a reserved register and should write only zeros to unmapped registers. Note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers.

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Contents General Description FeaturesBasic Block Diagram ApplicationsTable of Contents Specifications DC SpecificationsParameter Min Typ Max Unit Test Conditions/Comments Total Power Dissipation System Clock InputClock Output Drivers Parameter Min Typ Max Unit Test Conditions/Comments AC SpecificationsAvss − Parameter Rating Absolute Maximum RatingsThermal Resistance ESD CautionInput Pin No Output Pin Type Mnemonic Description PIN Configuration and Function DescriptionsOutb ResetIoupdate GND AvssVideo BW Typical Performance CharacteristicsAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Theory of Operation OverviewDirect Digital Synthesizer DDS 1024  DIGITAL-TO-ANALOG DAC OutputReconstruction Filter Solving this equation for FTW yieldsDAC Spectrum vs. Reconstruction Filter Response Fdbkin InputsSysclk Inputs Functional DescriptionSysclk PLL Doubler External Loop Filter Sysclk PLL Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core Detail of Sysclk Differential InputsHarmonic Spur Reduction Output Clock Drivers and 2× Frequency MultiplierSpur Reduction Circuit Diagram Thermal Parameters Thermal PerformancePOWER-UP POWER-ON ResetDefault Output Frequency on POWER-UP Supplies Power Supply PartitioningSerial Control Port Serial Control Port PIN DescriptionsOperation of Serial Control Port Operations are changed to LSB first order MSB/LSB First TransfersInstruction Word 16 Bits ReadI15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB FirstParameter Description PLL Register MAPHSR-A Register Descriptions Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Power-up default is defined by the start-up pinsRegister 0x0021-Reserved Register 0x0022-PLL Parameters Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0020-N-DividerRegister 0x0106-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0105-S-DividerRegister 0x01AC-Phase Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AB-FTW0 Frequency Tuning WordRegister 0x040D to Register 0x0410-Reserved Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040C-DAC Full-Scale CurrentRegister 0x0506-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0505-Spur BOutline Dimensions AD9912BCPZ-REEL71 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ1Rev. D Page 40