Analog Devices AD9912 specifications Serial Control Port, 16-Bit Instruction Word, MSB First

Page 28

AD9912

Table 10. Serial Control Port, 16-Bit Instruction Word, MSB First

MSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LSB

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1

I0

 

 

 

W1

W0

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CSB

SCLK DON'T CARE

SDIO DON'T CARE

 

 

 

 

 

 

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

 

R/W

W1

W0

A12

 

 

 

 

 

 

 

 

 

16-BIT INSTRUCTION HEADER

 

REGISTER (N) DATA

 

REGISTER (N – 1) DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 51. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data

CS

SCLK

DON'T CARE

SDIO

 

R/W

W1 W0

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

 

DON'T CARE

DON'T CARE

06763-043

DON'T CARE

SDO DON'T CARE

16-BIT INSTRUCTION HEADER

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

REGISTER (N) DATA

REGISTER (N – 1) DATA

REGISTER (N – 2) DATA

REGISTER (N – 3) DATA

DON'T

 

 

 

 

CARE

06763-057

Figure 52. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data

 

 

tS

tDS

 

tHI

tCLK

 

 

 

 

 

 

 

 

tH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDH

 

 

 

 

 

 

 

 

 

CSB

 

 

 

 

tLO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCLK

DON'T CARE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDIO

DON'T CARE

R/W

W1 W0 A12 A11 A10 A9

A8

A7

A6

A5

D4

D3

D2

D1

D0

 

 

 

Figure 53. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements

 

 

 

 

 

CSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDV

 

 

 

 

 

 

-046

 

 

 

 

 

 

SDIO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA BIT N

 

DATA BIT N – 1

 

 

 

06763

 

 

 

 

 

 

SDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DON'T CARE

DON'T CARE

06763-045

Figure 54. Timing Diagram for Serial Control Port Register Read

CSB

SCLK DON'T CARE

SDIO DON'T CARE

 

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

W0

W1

 

 

 

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

 

 

R/W

 

 

 

 

 

 

 

16-BIT INSTRUCTION HEADER

 

 

REGISTER (N) DATA

 

 

REGISTER (N + 1) DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 55. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data

DON'T CARE

DON'T CARE

06763-047

Rev. D Page 28 of 40

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Contents Features Basic Block DiagramApplications General DescriptionTable of Contents DC Specifications SpecificationsParameter Min Typ Max Unit Test Conditions/Comments System Clock Input Total Power DissipationClock Output Drivers AC Specifications Parameter Min Typ Max Unit Test Conditions/CommentsAvss − Absolute Maximum Ratings Thermal ResistanceESD Caution Parameter RatingPIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic DescriptionReset IoupdateGND Avss OutbTypical Performance Characteristics Video BWAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Overview Theory of OperationDirect Digital Synthesizer DDS DIGITAL-TO-ANALOG DAC Output Reconstruction FilterSolving this equation for FTW yields 1024 Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter ResponseFunctional Description Sysclk InputsSysclk PLL Doubler Sysclk PLL Multiplier Sysclk PLL multiplier has a 1 GHz VCO at its coreDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLLOutput Clock Drivers and 2× Frequency Multiplier Harmonic Spur ReductionSpur Reduction Circuit Diagram Thermal Performance Thermal ParametersPOWER-ON Reset POWER-UPDefault Output Frequency on POWER-UP Power Supply Partitioning SuppliesSerial Control Port PIN Descriptions Serial Control PortOperation of Serial Control Port MSB/LSB First Transfers Instruction Word 16 BitsRead Operations are changed to LSB first orderSerial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10Parameter Description Register MAP PLLHSR-A Register 0x0000-Serial Port Configuration Register 0x0010-Power-Down and EnablePower-up default is defined by the start-up pins Register DescriptionsRegister 0x0011-Reserved Register 0x0012-Reset Autoclearing Register 0x0013-Reset Not AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x01A7-FTW0 Frequency Tuning Word Register 0x01A8-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-DividerRegister 0x01A9-FTW0 Frequency Tuning Word Register 0x01AA-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x0200-HSTL Driver Register 0x0201-CMOS DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-ReservedRegister 0x0503-Spur a Register 0x0504-Spur aRegister 0x0505-Spur B Register 0x0506-Spur BOutline Dimensions Model Temperature Range Package Description Package Option Ordering GuideAD9912BCPZ1 AD9912BCPZ-REEL71Rev. D Page 40
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