Analog Devices AD9912 specifications Hsr-A

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AD9912

Addr

Type1

Default

(Hex)

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(Hex)

Calibration (user-accessible trim)

0x0400

Reserved

0x00

0x040A

0x040B

DAC full-

DAC full-scale current, Bits[7:0]

0xFF

0x040C

scale

DAC full-scale current,

0x01

current

Bits[9:8]

0x040D

Reserved

0x00

0x040E

Reserved

0x10

0x040F

Reserved

0x00

and

0x0410

Harmonic spur reduction

0x0500

Spur A

HSR-A

Amplitude

Spur A harmonic, Bits[3:0]

0x00

enable

gain × 2

0x0501

Spur A magnitude, Bits[7:0]

0x00

0x0503

Spur A phase, Bits[7:0]

0x00

0x0504

Spur A

0x00

phase, Bit 8

0x0505

Spur B

HSR-B

Amplitude

Spur B harmonic, Bits[3:0]

0x00

enable

gain × 2

0x0506

Spur B magnitude, Bits[7:0]

0x00

0x0508

Spur B phase, Bits[7:0]

0x00

0x0509

Spur B

0x00

phase, Bit 8

1Types of registers: M = mirrored (also called buffered). This type of register needs an I/O update for the new value to take effect; RO = read-only; AC = autoclear.

Rev. D Page 31 of 40

Image 31

Contents General Description FeaturesBasic Block Diagram ApplicationsTable of Contents DC Specifications SpecificationsParameter Min Typ Max Unit Test Conditions/Comments System Clock Input Total Power DissipationClock Output Drivers Parameter Min Typ Max Unit Test Conditions/Comments AC SpecificationsAvss − Parameter Rating Absolute Maximum RatingsThermal Resistance ESD CautionInput Pin No Output Pin Type Mnemonic Description PIN Configuration and Function DescriptionsOutb ResetIoupdate GND AvssVideo BW Typical Performance CharacteristicsAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Overview Theory of OperationDirect Digital Synthesizer DDS 1024  DIGITAL-TO-ANALOG DAC OutputReconstruction Filter Solving this equation for FTW yieldsDAC Spectrum vs. Reconstruction Filter Response Fdbkin InputsFunctional Description Sysclk InputsSysclk PLL Doubler External Loop Filter Sysclk PLL Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core Detail of Sysclk Differential InputsHarmonic Spur Reduction Output Clock Drivers and 2× Frequency MultiplierSpur Reduction Circuit Diagram Thermal Parameters Thermal PerformancePOWER-ON Reset POWER-UPDefault Output Frequency on POWER-UP Supplies Power Supply PartitioningSerial Control Port PIN Descriptions Serial Control PortOperation of Serial Control Port Operations are changed to LSB first order MSB/LSB First TransfersInstruction Word 16 Bits ReadI15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB FirstParameter Description PLL Register MAPHSR-A Register Descriptions Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Power-up default is defined by the start-up pinsRegister 0x0021-Reserved Register 0x0022-PLL Parameters Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0020-N-DividerRegister 0x0106-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0105-S-DividerRegister 0x01AC-Phase Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AB-FTW0 Frequency Tuning WordRegister 0x040D to Register 0x0410-Reserved Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040C-DAC Full-Scale CurrentRegister 0x0506-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0505-Spur BOutline Dimensions AD9912BCPZ-REEL71 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ1Rev. D Page 40